FAQ in Low Power

1. What are retention flops, where they are used?
2. what are isolation cells? where they are placed and why isolation's cells are used?
3. what is level shifter? what is use of level shifters?, where you will place them?
4. what is clock gating ?
5. what is power gating ?
6. what is MTCMOS switch, how will you place them?
7. what is UPF/CPF file, what kind of information it contain?
8. Difference between always ON and switchable domain?

IP in Vlsi

An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse , IP cores are part of the growing electronic design automation ( EDA ) industry trend towards repeated use of previously designed components. Ideally, an IP core should be entirely portable - that is, able to easily be inserted into any vendor technology or design methodology. Universal Asynchronous Receiver/Transmitter ( UART s), central processing units ( CPU s), Ethernet controllers, andPCI interfaces are all examples of IP cores.

IP cores fall into one of three categories: hard cores , firm cores , or soft cores . Hard cores are physical manifestations of the IP design. These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gate s and associated interconnections making up an integrated circuit ) or hardware description language ( HDL ) code.

A number of organizations, such as the Free IP Project and Open Cores, have formed to promote open sharing of IP cores.

What is capacitive loading? How does it affect slew rate?

By definition slew rate of a circuit is rate at which a circuit can charge and dischare 

capacitance. This capacitance may be external capacitor CL or  Cg gate 

capacitances of transistors connected to this circuit.  



Normally a digital circuit during switching must charge or discharge  CL or Cg at 

faster rate, and this charging rate depends on output current of the circuit.  



capacitive loading occurs when this output current is insufficient to drive load 

capacitances CL and one or more gates connected to original circuit as a result slew 

rate of the circuit decreases and circuit becomes slow(takes more time to charge 

capacitors connected to circuit).

Advantage and Disadvantage of using Asynchronous Reset

Advantages of using asynchronous reset

 Implementation of asynchronous reset requires less number of gates compared to 

synchronous reset design.

 Asynchronous reset is fast.

 Clocking scheme is not necessary for an asynchronous design. Hence design 

consumes less power. Asynchronous design style is also one of the latest design 

options to achieve low power. Design community is scrathing their head over 

asynchronous design possibilities.

 Disadvantages of using asynchronous reset 

 Metastability problems are main concerns of asynchronous reset scheme (design). 

 Static timing analysis and DFT becomes difficult due to asynchronous reset.

Manufacture of SOI wafers

SiO₂-based SOI wafers can be produced by several methods:

• SIMOX - Separation by IMplantation of OXygen – uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO₂layer.

• Wafer bonding – the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
  • One prominent example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
  • NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.
  • ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.
• Seed methods- wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

References

1.https://en.wikipedia.org/wiki/Silicon_on_insulator#/media/File:Smart_Cut_SOI_Wafer_Manufacturing_Schema.svg

2. https://en.wikipedia.org/wiki/Silicon_on_insulator

Industrial Need of SOI

 Industrial Need of SOI

The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:

• Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
• Resistance to latchup due to complete isolation of the n- and p-well structures.
• Higher performance at equivalent VDD. Can work at low VDD's.
• Reduced temperature dependency due to no doping.
• Better yield due to high density, better wafer utilization.
• Reduced antenna issues
• No body or well taps are needed.
• Lower leakage currents due to isolation thus higher power efficiency.
• Inherently radiation hardened ( resistant to soft errors ), thus reducing the need for redundancy.

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.

References

1. https://en.wikipedia.org/wiki/Silicon_on_insulator

Silicon on Insulator

Introduction

Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

References

1. https://en.wikipedia.org/wiki/Silicon_on_insulator#/media/File:SIMOX_processing_schematic.svg

2. https://en.wikipedia.org/wiki/Silicon_on_insulator

FinFET

finFET seems to be the most promising and disruptive technology at the moment able to mantain the Moore’s Law trend and expectations. The most active players (IDM, Foundries, EDA companies and IP providers) in the semiconductor market are putting a lot of effort, investments and emphasis on this hot topic.

For this reason I decided to collect information and share a post regarding this technology. It’s not anymore the time for me to enter in mathematical and physical details, but my interest  is to understand the reasons and the advantages of the FinFET technology from a marketing perspective.

Reasons

The Moore’s Law and the market are pushing constantly to increase the density of transistors in chip and the performances in term of speed and power consumption. This scaling process seems to be at a technology limit for the planar transistor with length below 20nm: the electrical parameters start degrading and the silicon process variations impact heavily in the performances. The main reason of this degradation is due to the planar structure itself: the gate does not have a good electrostatic field control away from the surface of the channel. With geometry scaling,  it brings to:

• Lower current in the channel
• Leakage current drain-source when the transistor is theoretically switched off 
• Short channel effect
• High dependence on process variations (Vth and swing).

Solution

The solution seems to be indeed the 3D approach:  the channel between source and drain is built as a three-dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped around the channel, so the gate can control the channel electrical field. In this structure, the gate can control much better the electrical field in the 3D channel.

Several options and enhancement are proposed. In the picture below a finFET has been built on SOI with a further reduction of current leakage. There can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.

Advantages

FinFET technology impacts all the electrical parameters of the transistor and you have benefit in power consumption (static and dynamic), speed and voltage supply range. FinFETs also improve the always challenging tradeoff between performance and power: you can go faster with the same amount of power, compared to the planar equivalent, or save power at the same speed. In a list, the promised advantages over plan transistor:

• Higher drain current
• up to 37% switching speed
• Lower switching voltage
• less than half the dynamic power
• 90% less static leakage current

The above points reached with a low cost impact: leading foundries estimate the additional processing cost of 3D devices to be 2% to 5% higher than that of the corresponding Planar wafer fabrication.

State of the Art

Almost all the big players in the semiconductor eco-system are focusing on the finFET technology, so news, announcements and updates come out every day.

The finFET era started  in 2011, when Intel unveiled the newfangled transistor technology at the 22nm node (now in production). Intel plans are to ramp up its second-generation finFET devices at 14nm by year’s end and move to 11nm by 2015.

Silicon Foundries are already defining their plans with finFETs technology. GlobalFoundries will deliver14nm finFET by 2014 and 10nm finFet by 2015. TSMC is planning to deliver 16nm finFET by 2014.

EDA player are dedicating big effort to model this complex device and to deliver compelling design tools to designers. In particular Synopsys is working hard to deliver tools and IP for FinFET design, as in the news.

Conclusion

Maybe we are at the beginning of a new era. finFETs can potentially determinate a big step forward in the never ending effort to reduce power consumption, to increase switching speed and number of transistors. Always with a cost reduction.

Refrerences

1. https://en.m.wikipedia.org/wiki/FinFET#FINFET

2. https://cologneseandrea.wordpress.com/2013/03/20/finfet-technology-for-dummies-like-me/