Showing posts with label DFT. Show all posts
Showing posts with label DFT. Show all posts

Tuesday, 8 April 2025

Stuck-at Faults


"Stuck-at faults" are a type of fault model used in digital circuit testing to simulate common types of defects that can occur in hardware.


What are Stuck-At Faults?

A stuck-at fault assumes that a signal line (such as a wire or a gate output) is "stuck" at a constant logic level, regardless of the actual input or expected behavior.

There are Two Types :

Stuck-at-0 (SA0): The node is stuck at logic 0.

Stuck-at-1 (SA1): The node is stuck at logic 1.


Why use stuck-at fault models?

They are a simplified and effective model for:

  • Testing digital circuits (to ensure manufacturing defects don't break the logic).

  • Fault simulation and automatic test pattern generation (ATPG).


Example

Imagine this logic:






Normally, Z = A AND B.

If input A is stuck-at-0 (SA0), then:

  • No matter the value of B, Z will always be 0.

  • This is a fault, and testing should catch it.


In Testing

  • Stuck-at fault testing helps in detecting defects like:

    • Broken wires

    • Transistor failures

    • Short circuits

  • It's the most commonly used model in combinational and sequential logic testing.





Monday, 7 April 2025

What is DFT?

What is DFT ?

DFT stands for Design for Testability. It's a set of design techniques used in digital integrated circuit (IC) design to make it easier to test whether a chip is working correctly after manufacturing.


Why DFT is needed:

Chips are super complex (millions to billions of transistors).

Manufacturing defects can occur.

You can’t manually test every internal signal.

So, you need built-in mechanisms to test them automatically.


Common DFT techniques:

Scan Chains – Makes internal flip-flops accessible for testing.

ATPG (Automatic Test Pattern Generation) – Tools generate test vectors to detect faults.

BIST (Built-In Self Test) – Circuit tests itself using internal logic.

Boundary Scan (JTAG) – Used to test interconnections between chips on a board.


Goal of DFT:

Improve test coverage.

Reduce test time.

Enable early detection of defects, saving time and cost in production.

Automatic Test Pattern Generation (ATPG)



What is ATPG ?

 

ATPG stands for Automatic Test Pattern Generation. It is a DFT (Design for Testability) technique used to create test patterns that can detect manufacturing defects in an integrated circuit (IC).


What Does ATPG Do?

ATPG tools analyze the gate-level netlist of a chip and generate test vectors (input patterns and expected outputs) to:

  • Detect stuck-at faults (e.g., a net stuck at 0 or 1)
  • Detect transition delay faults
  • Improve fault coverage for logic defects

These patterns are later applied using scan chains during testing on Automatic Test Equipment (ATE).

 

ATPG Flow in VLSI

  1. DFT Insertion
    • Add scan chains, test logic (e.g., muxed flip-flops), and test controllers.
  2. Fault Modeling
    • Define fault models like stuck-at, transition, path delay, bridging faults, etc.
  3. Pattern Generation
    • Generate input stimulus to propagate faults to observable outputs.
  4. Pattern Compression (optional)
    • Compress patterns to reduce test time and memory.
  5. Test Coverage Analysis
    • Check % of faults detected.
  6. Pattern Export
    • Export to a tester format (like STIL, WGL, or VCD).



Fault Models

Fault Type

Description

Stuck-at Faults

Signal stuck at 0 or 1 regardless of logic

Transition Faults

Detect slow-to-rise or slow-to-fall faults

Bridging Faults

Two signals are shorted

Path Delay Faults

Delay on a particular path



🔧 Tools Used

·       Popular ATPG tools include:

·       Synopsys TetraMAX / TetraMAX II

·       Mentor Tessent

·       Cadence Modus

 

📊 Why ATPG is Important

·       Increases manufacturing test quality

·       Helps detect defective chips before packaging

·       Achieves high fault coverage (~99% for stuck-at)

·       Reduces field failure rates


Friday, 25 September 2015

Companies works in VLSI

Today, VLSI jobs are one of the highly paid occupation of the world, I have tried to figure out some of the companies which are working in VLSI domain. If you are interested in physical design send your resume at  vlsijunction@gmail.com

  1. AMD
  2. Aricent
  3. Alten
  4. Altran
  5. Analog Devices (India) Pvt. Ltd. 
  6. Blackpepper 
  7. BLR Labs
  8. Broadcom India 
  9. Cisco
  10. Cypress Semiconductors
  11. Cyient
  12. einfochip
  13. Global Foundries
  14. Graphene Semiconductors
  15. HCL Technologies India Pvt. Ltd.
  16. IBM
  17. Infineon Technologies India Pvt. Ltd.
  18. Intel
  19. Invecas
  20. Microsemi
  21. mirafra
  22. Mindlance
  23. MosChip Semiconductor Technology Ltd.
  24. Sasken Communications Technologies Ltd.
  25. Sankalp Semiconductors
  26. ST Microelectronics Ltd.
  27. Tata Elxsi
  28. Texas Instruments (India) Ltd.
  29. Wipro Ltd.
  30. Whizchip
  31. Xilinx        

and Many More companies are there......