Physical Design Flow

Physical Design Flow

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.

Modern day Integrated Circuit (IC) design is split up into Front-end design using HDL's, Verification and Back-end Design or Physical Design. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs.

Each of the phases mentioned above have Design Flows associated with them. These Design Flows lay down the process and guide-lines/framework for that phase. Physical Design flow uses the technology libraries that are provided by the fabrication houses. These technology files provide information regarding the type of Silicon wafer used, the standard-cells used, the layout rules, etc.

Technologies are commonly classified according to minimal feature size. Standard sizes, in the order of miniaturization, are 2μm, 1μm , 0.5μm , 0.35μm, 0.25μm, 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 18nm... They may be also classified according to major manufacturing approaches: n-Well process, twin-well process, SOI process, etc.

The main steps in the flow are:

• Design Netlist (after synthesis)

• Floor Planning

• Partitioning

• Placement

• Clock-tree Synthesis (CTS)

• Routing

• Physical Verification

• GDS II Generation

These steps are just the basic. There are detailed PD Flows that are used depending on the Tools used and the methodology/technology. Some of the tools/software used in the back-end design are :

• Cadence (SOC Encounter, VoltageStorm, NanoRoute)

• Synopsys (Design Compiler, IC Compiler, PrimeTime)

• Magma (BlastFusion, Talus )

• Mentor Graphics (Olympus SoC, IC-Station, Calibre)     

 
 
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List of Topics

Topics                                                                             Date of Last Update

1. Floor Planning .......................................................................      22 Aug 2015
2. Power Planning  .....................................................................      7 Aug 2015
3.  Placement ...............................................................................     8 Aug 2015
4.  Clock Tree Synthesis ..............................................................     8 Aug 2015
5.  Routing ...................................................................................     8 Aug 2015
6.  Static Timing Analysis ...........................................................      8 Aug 2015
7.  Physical Verification ..............................................................      8 Aug 2015
8.  Impotant Input Files ...............................................................      6 Aug 2015
9.  IC Compiler Tutorial ..............................................................     15 Aug 2015
10.  Physical Design Flow ...........................................................   19 Aug 2015
11.  Types of cells used in Physical Design ................................    20 Aug 2015
12.  Basics of Linux Commands .................................................     21 Aug 2015
13.  Double patterning..................................................................    22 Aug 2015
14.  Advance Onchip variations (AOCV) ......................................    22 Aug 2015
15.  Statistical Static timing Analysis .............................................    18 Sep 2015
16.  Sanity Checks .........................................................................   7 Oct 2015
17.  Signal integrity in ASIC ...........................................................   7 Oct 2015
18.  Interview Questions .................................................................  17 Oct 2015
19.  Non Default Rules (NDR Rules) ...............................................  17 Oct 2015
20.  Antennae Effects .......................................................................  17 Oct 2015
21.  Crosstalk ....................................................................................  17Oct 2015
22.  DEF files ....................................................................................  17Oct 2015
23. LEF files ....................................................................................   17Oct 2015
24. Low Power Design Techniques
25. CMOS Fundamentals
26. Interview Questions

List of Topics Coming Soon

1. Checks need to be done before each steps
2. Latch Up Effect
3. Electrostatic Discharge (ESD)
4. Basics of DFT
5. Basics of Synthesis
6. Advance STA concepts