Saturday, 8 August 2015



After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to let the tool to do standard cell placement. The tool determines the location of each of the components (in digital design, standard cell instantiations) on the die. Various factors come into play, like the timing requirement of the system, the interconnect lengths and hence the connections between cells, power dissipation etc. The interconnect lengths depend on the placement solution used, and it is very important in determining the performance of the system as the geometries shrink. Placement also determines the routability of your design.
Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design, thereby removing any timing violations created due to the relative placement on die.

Inputs To Placement Stage

  •  Netlist
  • Mapped and Floorplannned Design
  • Logical and Physical Libraries
  • Design Constraints

Output of Placement Stage

  • Physical Layout Information
  • Cell placement location
  • Physical Layout, timing, and technology information of logical libraries

Below are key task perfomed during Placement stage

1. Special Cell Placement :- Placement of Well-Tap Cells, End-Cap Cells, Spare Cells, Decap Cells, JTAG and Other Cells Close to the I/Os

2. Optimizing and Reordering Scan Chains

3. Plaement Methodology :- Congestion Driven Placement Timing Driven Placement

4. Logic optimization In Placement

5. Major Placement Steps :- Virtual Placement, HFN synthesis, Initial (Global) Placement, Detailed, placement (Legalization) –Refine Placement

Post Placement Analysis-

1. Timing, Congestion Analysis

2. Placement Congestion: cell density

3. Global Route Congestion

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