Wednesday, 5 June 2019

How many macros and standard cell were there in your block?

Answer to this question is purely on the design specific, bu there are blocks without macros also, which is called purely standard cell cells blocks. As number of macros increased, analysis in the floor plan also increases, below are some checks which you have to do while handling large number of macro
1. Legalization of macros
2. connectivity of macros to standard cells, other macro and ports, ignoring of this point may cause the congestion and timing violation
3. while arranging the macros in floorplan consider macro to macro communication also
4. always keep some channel between the macro, in later stages this will help in hold buffering,

what is SDF files?

Standard Delay Format (SDF) is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between dynamic timing verification and static timing analysis.
It was originally developed as an OVI standard, and later modified into the IEEE format. Technically only the SDF version 4.0 onwards are IEEE formats.
It is an ASCII format that is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.
It has usually two sections: one for interconnect delays and the other for cell delays.
SDF format can be used for back-annotation as well as forward-annotation.

The Standard Delay Format (SDF) file stores the timing data generated by
EDA tools for use at any stage in the design process. The data in the SDF
file is represented in a tool-independent way and can include
  •  Delays: module path, device, interconnect, and port
  •  Timing checks: setup, hold, recovery, removal, skew, width, period, and nochange
  •  Timing constraints: path, skew, period, sum, and diff
  •  Timing environment: intended operating timing environment
  •  Incremental and absolute delays
  •  Conditional and unconditional module path delays and timing checks
  •  Design/instance-specific or type/library-specific data
  •  Scaling, environmental, and technology parameters

Throughout a design process, you can use several different SDF files. Some of these files can contain pre-layout timing data. Others can contain path constraint or post-layout timing data. The name of each SDF file is determined by the EDA tool. There are no conventions for naming SDF files.

Friday, 31 May 2019

Product, EDA, Foundaries and service Companies that works in the field of VLSI

List of few Product companies, EDA companies and Foundaries who works in the field of VLSI, there are many companies but the popular ones captured here . There are many good service companies which works in VLSI domain,

Product Companies

  • AMD
  • Analog Devices
  • Apple
  • ARM
  • Broadcom
  • Cisco
  • Cypress Semiconductors
  • Google
  • Infineon Technologies AG
  • Intel
  • LG Soft
  • Microsemi
  • MosChip Semiconductor Technology Ltd
  • Nvidia
  • NXP
  • ON Semiconductor
  • Qualcomm
  • Samsung Electronics
  • STMicroelectronics
  • Texas Instrument
  • Western Digital

EDA Companies

  • Ansys
  • Cadence
  • Dorado
  • Mentor Graphics
  • Synosys
  • Xilinx


  • Global Foundaries
  • Intel
  • Samsung
  • TSMC
  • UMC

Top Service Companies

  • Atran
  • cientra
  • einfochip
  • Eximius
  • L & T
  • Mirafra
  • Open-Silicom
  • Open-Silicon
  • Sankalp semiconductor
  • Synapse Design
  • UST Global
  • whizchip
  • Wipro

Thursday, 30 May 2019

What is Objective and challenges of Physical Design?

Since design and manufacturing of IC (Integrated circuits) could millions of dollars. Quality of chip also matters a lot to company. 

AIM of Physical design Engineer to acieve 
  •  Power
  •  Performance
  •  Area

This target is also known as PPA,

Saving of power (dynamic and static) lesser the heating of the circuit. If chip is going to be in battery operated system then power consumed by IC significantly results in battery drained off. less the power more time battery can run operate the device.

Performance term is associated with speed/frequency or we can say timing, faster the circuit performance will be greats.

Cost of manufacturing is directly proportional to area, if area of IC is more than more cost you need to pay to manufacturer. In order to save money in manufacturing preferable is more number of gate counts should be get manufacture in given amount of area.

Challenges in Physical design
  •  Achieve timing
  •  Congestion
  •  Manufacturing requirements such as DRC, DFM etc
  •  Meeting power numbers
  •  Delivery of the project timelines

As technology nodes is shrinking achieving above targets are becoming tougher and tougher. Identifying the issues at early stages is always good. In order to achieve target keep running sign off checks at regular interval of time. Re-spin of design is time consuming and non-productive way of working.

Every company aims to bring their product in market as soon as possible in order to beat the competition. So keeping in the mind objective and challenges a physical design engineer should work.

What is Physical Design?

The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components.

The main steps in the ASIC physical design flow are:

  • Design Netlist (after synthesis)
  • Floorplanning
  • Partitioning
  • Placement
  • Clock-tree Synthesis (CTS)
  • Routing
  • Physical Verification
  • GDS II Generation

Below are main sign off checks/Analysis in Physical Design

  • 1. Logical Equivalence Check
  • 2. Static Timing Analysis
  • 3. Power analysis (static and dynamic,  resistance checks etc)
  • 4. Low power Checks

Saturday, 25 May 2019

Crosstalk in Physical Design

Crosstalk is the undesirable electrical interaction between two or more physically adjacent nets due to capacitive cross-coupling. As integrated circuit technologies advance toward smaller geometries, crosstalk effects become increasingly important compared to cell delays and net delays.

How to fix cross talk

1. using NDR (eg. double width and double spacing) rules on Nets
2. increase the drive strength of the driver cell of victim net
3. shielding can be one of the option 
4. Breaking the net by buffer insertion
5. Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur.

Tuesday, 8 January 2019

Skill Set Required for a Physical Design Engineer

As a Physical Design Engineer Market expect the following Skill set.

1. fair knowledge of physical desgn flow, Which include RTL Synthesis, Floorplanning, Placement of cells, Clock Tree Synthesis, Routing.
2. knowledge of Sign off checks like Static Timing Analysis, IR drop checks, Physical verification Checks, Logical Equivalence checks, Low Power checks
3. Scripting Languages Like Perl, TCL etc.
4. EDA Tool knowledge, Mostly tools from Synopsys and cadence are used in Physical Design.

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Moore's second law

As the cost of computer power to the consumer falls, the cost for producers to fulfill Moore's law follows an opposite trend: R&D, manufacturing, and test costs have increased steadily with each new generation of chips. Rising manufacturing costs are an important consideration for the sustaining of Moore's law. This had led to the formulation of Moore's second law, also called Rock's law, which is that the capital cost of a semiconductor fab also increases exponentially over time.

Moore's Law

Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years. The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and CEO of Intel, whose 1965 paper described a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years. The period is often quoted as 18 months because of a prediction by Intel executive David House (being a combination of the effect of more transistors and the transistors being faster).