Monday 23 December 2019

Question which were asked on 22nd dec session (doubts clearing session)

  1. Difference between flat and hierarchical design?
  2. What is the need for sanity checks at floorplan stage?
  3. Explanation of flipchip?
  4. How can we decide no of routing layers in a design? Does more no of routing layers beneficial.
  5. Difference between drive strength and fanout.
  6. For specific corner can a path have both setup and hold violation?
  7. Why do we have no of routing layers better or worse?
  8. What is functional ECO?
  9. Difference SDC file as an input to floor planning although we don’t do timing analysis after floor planning?
  10. How to decide max transition on clock and data?
  11. What is RDL layer?
  12. Two clock paths coming from same PLL will always be synchronous or asynchronous? Or are there different conditions attached to it.
  13. Why do we need driving cell for input ports and load for the output ports?
  14. Is there any difference between tie cells and level shifters?
  15. Why setup is only considered for worst case? and Hold for best case? and What will happen if reverse is done?
  16. Explanation regarding capture and launch clock.
  17. Difference between HFNS and CTS.  
  18. how std cells are placed? With complete explanation?
  19. how to resolve unsigned nets in the synthesis stage?
  20. how to resolve max tran and max cap vailotions?
  21. implicite and explicit exceptions in cts stage?
  22. Input files based on Physical Design (Indeep and explain with those files?
  23. Synchronizer Logic With Example?
  24. Frequency divider for 3,4,5,6,7,8?
  25. When we ar eworking  90nm or other tech  how to change  one technology to another technology or else for given technology is fixed we can't  change for a same project
  26. how to fix drc
  27. is drc and crpr related

Sunday 15 December 2019

Why DFT Logic is required in VLSI flow?

DFT stands for Design for testability. This is require because of following reasons

1. To validate the functionality of the chip
2. DFT is very important in  diagnostics and testing of chip
3. DFT ensure early fault detection which saves the reputation of chip manufaturer, and ensuring functioning of chip before coming to the hand of customer

How Testing is done?

1. Test Patterns are being generated and that test patterns are given to design under test (DUT) as vector. if the result of test pattern and result of vector which is given to DUT matched then chip is manufatured without defects.

Common Method to implement DFT logic 

1. Scan Chain
2. ATPG (Automatic Test pattern Generation)

Friday 29 November 2019

Basic Synthesis Flow

Logic Synthesis means converting RTL (Register Transfer Level) into logic gates with the help of synthesis tool. Design compiler by Synopys is an example of synthesis tool and it is one of the widely used tool across the industries. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

Thursday 28 November 2019

Generation of Integrated Circuits

As number of transistor, which can be fabricated in a single chip increased through generation, We believe more transistor and more complex IC's are yet to come.

SSI  (Small Scale Integration) introduced in 1964, Having transistors 1 - 10 and logic gates 1 - 12

MSI (Medium Scale Integration) introduced in 1968, Having transistors 10 - 500 and logic gates  13 - 99

LSI (Large Scale Integration) introduced in 1971, having transistors 500 - 20000 and logic gates 100 - 9999

VLSI (Very Large Scale Integeration) introduced in 1980, having transistors 20000-1000000 and logic gates 10000 to 99999

ULSI (Ultra Large Scale Integration) introduced in 1984, having transistor 1000000 and more and logic gates 100000 and more

WSI (Wafer Scale Integration) is a means of building very large integrated circuits that uses an entire silicon wafer to produce a single "super-chip".

SoC or SOC (System On Chip) is an integrated circuit in which all the components needed for a computer or other system are included on a single chip.

3D-IC (3 Dimensional Integrated Circuit) has two or more layers of active electronic components that are integrated both vertically and horizontally into a single circuit.

NameSignificationYearTransistors numberLogic Gates number
SSIsmall-scale integration19641 to 101 to 12
MSImedium-scale integration196810 to 50013 to 99
LSIlarge-scale integration1971500 to 20 000100 to 9999
VLSIvery large-scale integration198020 000 to 1 000 00010 000 to 99 999
ULSIultra-large-scale integration19841 000 000 and more100 000 and more

Wednesday 27 November 2019

Metal Slotting


In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)– have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future placeand-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop.

A wider wire results in smaller current density and, hence, less likelihood of electromigration. Also, the metal grain size has influence; the smaller grains, the more grain boundaries and the higher likelihood of electromigration effects. However, if you reduce wire width to below the average grain size of the wire material, grain boundaries become "crosswise", more or less perpendicular to the length of the wire. The resulting structure resembles the joints in a stalk of bamboo. With such a structure, the resistance to electromigration increases, despite an increase in current density. This apparent contradiction is caused by the perpendicular position of the grain boundaries; the boundary diffusion factor is excluded, and material transport is correspondingly reduced.

However, the maximum wire width possible for a bamboo structure is usually too narrow for signal lines of large-magnitude currents in analog circuits or for power supply lines. In these circumstances, slotted wires are often used, whereby rectangular holes are carved in the wires. Here, the widths of the individual metal structures in between the slots lie within the area of a bamboo structure, while the resulting total width of all the metal structures meets power requirements.

What is the Need of Metal slotting

  1. To maintain the reliability during manufacturing
  2. To overcome mechanical and thermal stress during manufacturing

How Metal slotting is done

  1. Determining long and wide wires, based on foundry rules and foundry capability to manufacture
  2. Place and route tools perform metal filing and slotting with utmost optimization

Wednesday 5 June 2019

How many macros and standard cell were there in your block?

Answer to this question is purely on the design specific, bu there are blocks without macros also, which is called purely standard cell cells blocks. As number of macros increased, analysis in the floor plan also increases, below are some checks which you have to do while handling large number of macro
1. Legalization of macros
2. connectivity of macros to standard cells, other macro and ports, ignoring of this point may cause the congestion and timing violation
3. while arranging the macros in floorplan consider macro to macro communication also
4. always keep some channel between the macro, in later stages this will help in hold buffering,

what is SDF files?

Standard Delay Format (SDF) is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between dynamic timing verification and static timing analysis.
It was originally developed as an OVI standard, and later modified into the IEEE format. Technically only the SDF version 4.0 onwards are IEEE formats.
It is an ASCII format that is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.
It has usually two sections: one for interconnect delays and the other for cell delays.
SDF format can be used for back-annotation as well as forward-annotation.

The Standard Delay Format (SDF) file stores the timing data generated by
EDA tools for use at any stage in the design process. The data in the SDF
file is represented in a tool-independent way and can include
  •  Delays: module path, device, interconnect, and port
  •  Timing checks: setup, hold, recovery, removal, skew, width, period, and nochange
  •  Timing constraints: path, skew, period, sum, and diff
  •  Timing environment: intended operating timing environment
  •  Incremental and absolute delays
  •  Conditional and unconditional module path delays and timing checks
  •  Design/instance-specific or type/library-specific data
  •  Scaling, environmental, and technology parameters

Throughout a design process, you can use several different SDF files. Some of these files can contain pre-layout timing data. Others can contain path constraint or post-layout timing data. The name of each SDF file is determined by the EDA tool. There are no conventions for naming SDF files.

Friday 31 May 2019

Product, EDA, Foundaries and service Companies that works in the field of VLSI

List of few Product companies, EDA companies and Foundaries who works in the field of VLSI, there are many companies but the popular ones captured here . There are many good service companies which works in VLSI domain,

Product Companies

  • AMD
  • Analog Devices
  • Apple
  • ARM
  • Broadcom
  • Cisco
  • Cypress Semiconductors
  • Google
  • Infineon Technologies AG
  • Intel
  • LG Soft
  • Microsemi
  • MosChip Semiconductor Technology Ltd
  • Nvidia
  • NXP
  • ON Semiconductor
  • Qualcomm
  • Samsung Electronics
  • STMicroelectronics
  • Texas Instrument
  • Western Digital

EDA Companies

  • Ansys
  • Cadence
  • Dorado
  • Mentor Graphics
  • Synosys
  • Xilinx


  • Global Foundaries
  • Intel
  • Samsung
  • TSMC
  • UMC

Top Service Companies

  • Atran
  • cientra
  • einfochip
  • Eximius
  • L & T
  • Mirafra
  • Open-Silicom
  • Open-Silicon
  • Sankalp semiconductor
  • Synapse Design
  • UST Global
  • whizchip
  • Wipro

Thursday 30 May 2019

What is Objective and challenges of Physical Design?

Since design and manufacturing of IC (Integrated circuits) could millions of dollars. Quality of chip also matters a lot to company. 

AIM of Physical design Engineer to acieve 
  •  Power
  •  Performance
  •  Area

This target is also known as PPA,

Saving of power (dynamic and static) lesser the heating of the circuit. If chip is going to be in battery operated system then power consumed by IC significantly results in battery drained off. less the power more time battery can run operate the device.

Performance term is associated with speed/frequency or we can say timing, faster the circuit performance will be greats.

Cost of manufacturing is directly proportional to area, if area of IC is more than more cost you need to pay to manufacturer. In order to save money in manufacturing preferable is more number of gate counts should be get manufacture in given amount of area.

Challenges in Physical design
  •  Achieve timing
  •  Congestion
  •  Manufacturing requirements such as DRC, DFM etc
  •  Meeting power numbers
  •  Delivery of the project timelines

As technology nodes is shrinking achieving above targets are becoming tougher and tougher. Identifying the issues at early stages is always good. In order to achieve target keep running sign off checks at regular interval of time. Re-spin of design is time consuming and non-productive way of working.

Every company aims to bring their product in market as soon as possible in order to beat the competition. So keeping in the mind objective and challenges a physical design engineer should work.

What is Physical Design?

The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components.

The main steps in the ASIC physical design flow are:

  • Design Netlist (after synthesis)
  • Floorplanning
  • Partitioning
  • Placement
  • Clock-tree Synthesis (CTS)
  • Routing
  • Physical Verification
  • GDS II Generation

Below are main sign off checks/Analysis in Physical Design

  • 1. Logical Equivalence Check
  • 2. Static Timing Analysis
  • 3. Power analysis (static and dynamic,  resistance checks etc)
  • 4. Low power Checks

Saturday 25 May 2019

Crosstalk in Physical Design

Crosstalk is the undesirable electrical interaction between two or more physically adjacent nets due to capacitive cross-coupling. As integrated circuit technologies advance toward smaller geometries, crosstalk effects become increasingly important compared to cell delays and net delays.

How to fix cross talk

1. using NDR (eg. double width and double spacing) rules on Nets
2. increase the drive strength of the driver cell of victim net
3. shielding can be one of the option 
4. Breaking the net by buffer insertion
5. Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur.

Tuesday 8 January 2019

Skill Set Required for a Physical Design Engineer

As a Physical Design Engineer Market expect the following Skill set.

1. fair knowledge of physical desgn flow, Which include RTL Synthesis, Floorplanning, Placement of cells, Clock Tree Synthesis, Routing.
2. knowledge of Sign off checks like Static Timing Analysis, IR drop checks, Physical verification Checks, Logical Equivalence checks, Low Power checks
3. Scripting Languages Like Perl, TCL etc.
4. EDA Tool knowledge, Mostly tools from Synopsys and cadence are used in Physical Design.

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Moore's second law

As the cost of computer power to the consumer falls, the cost for producers to fulfill Moore's law follows an opposite trend: R&D, manufacturing, and test costs have increased steadily with each new generation of chips. Rising manufacturing costs are an important consideration for the sustaining of Moore's law. This had led to the formulation of Moore's second law, also called Rock's law, which is that the capital cost of a semiconductor fab also increases exponentially over time.

Moore's Law

Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years. The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and CEO of Intel, whose 1965 paper described a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years. The period is often quoted as 18 months because of a prediction by Intel executive David House (being a combination of the effect of more transistors and the transistors being faster).