Monday 28 September 2015

Sanity Checks

We need to perform some sanity checks before we start our physical design flow, Sanity check will ensure that input which we received from various team such as synthesis team, library team etc are correct. If we missed this checks than it can create problem in later stage.
Below are input fies which we are mainly checking
1. Netlist
2. SDC Files
3. Library Files
4. Design Data

Saturday 26 September 2015

Transistor Sizing

First of all, let us consider the sizing of an inverter. We have already seen that the propagation delay of the gate is proportional to (Rp + Rn)CL. The delay of an inverter can be minimized by keeping the output capacitance small or by decreasing the on resistance of the transistor. The Cconsists of the diffusion capacitance of the transistors, the interconnect capacitance and the fan-out capacitance. Careful layout helps to reduce the diffusion and interconnect capacitances. The on-resistance of the transistor is inversely proportional to the W/L ratio of the device. It is known that the mobility of holes are approximately 2.5 times lower than that of electrons in Silicon. Thus, a 2.5 time wider PMOS transistor is needed to match its on-resistance to that of pull-down NMOS device. With such a sizing of NMOS and PMOS width, we can design an inverter with a symmetrical VTC (Voltage Transfer Characteristics) and equal high-to-low and low-to-high propagation delays. The diffusion capacitance is also increased with increasing widths and careful optimization is required.


Wafer Fabrication Techniques

Wafer fabrication is a procedure composed of many repeated sequential processes to produce completeelectrical or photonic circuits. Examples include production of radio frequency (RF) amplifiers, LEDs, optical computer components, and CPUs for computers. Wafer fabrication is used to build components with the necessary electrical structures.

The main process begins with electrical engineers designing the circuit and defining its functions, and specifying the signals, inputs, outputs and voltages needed. These electrical circuit specifications are entered into electrical circuit design software, such as SPICE, and then imported into circuit layout programs, which are similar to ones used for computer aided design. This is necessary for the layers to be defined for photomask production. The resolution of the circuits increases rapidly with each step in design, as the scale of the circuits at the start of the design process is already being measured in fractions of micrometers. Each step thus increases circuit density for a given area.

The silicon wafers start out blank and pure. The circuits are built in layers in clean rooms. First, photoresistpatterns are photo-masked in micrometer detail onto the wafers' surface. The wafers are then exposed to short-wave ultraviolet light and the unexposed areas are thus etched away and cleaned. Hot chemical vapors aredeposited on to the desired zones and baked in high heat, which permeate the vapors into the desired zones. In some cases, ions, such as O2+ or O+, are implanted in precise patterns and at a specific depth by using RF-driven ion sources.

These steps are often repeated many hundreds of times, depending on the complexity of the desired circuit and its connections.

New processes to accomplish each of these steps with better resolution and in improved ways emerge every year, with the result of constantly changing technology in the wafer fabrication industry. New technologies result in denser packing of minuscule surface features such as transistors and micro-electro-mechanical systems (MEMS). This increased density continues the trend often cited as Moore's Law.

A fab is a common term for where these processes are accomplished. Often the fab is owned by the company that sells the chips, such as AMD, Intel, Texas Instruments, or Freescale. A foundry is a fab at which semiconductor chips or wafers are fabricated to order for third party companies that sell the chip, such as fabs owned by Taiwan Semiconductor Manufacturing Company (TSMC), United Microelectronics Corporation (UMC) and Semiconductor Manufacturing International Corporation (SMIC).


CMOS Fundamentals

Before Going through complete physical design course one need to know basic fundamentals of CMOS, which will help you to understand other advance concept easi

Friday 25 September 2015

Parametric On chip variation (POCV)

Will be published shortly,

please do write in comment section, if the topic which you are looking for is not covered in this blog

Companies works in VLSI

Today, VLSI jobs are one of the highly paid occupation of the world, I have tried to figure out some of the companies which are working in VLSI domain. If you are interested in physical design send your resume at

  1. AMD
  2. Aricent
  3. Alten
  4. Altran
  5. Analog Devices (India) Pvt. Ltd. 
  6. Blackpepper 
  7. BLR Labs
  8. Broadcom India 
  9. Cisco
  10. Cypress Semiconductors
  11. Cyient
  12. einfochip
  13. Global Foundries
  14. Graphene Semiconductors
  15. HCL Technologies India Pvt. Ltd.
  16. IBM
  17. Infineon Technologies India Pvt. Ltd.
  18. Intel
  19. Invecas
  20. Microsemi
  21. mirafra
  22. Mindlance
  23. MosChip Semiconductor Technology Ltd.
  24. Sasken Communications Technologies Ltd.
  25. Sankalp Semiconductors
  26. ST Microelectronics Ltd.
  27. Tata Elxsi
  28. Texas Instruments (India) Ltd.
  29. Wipro Ltd.
  30. Whizchip
  31. Xilinx        

and Many More companies are there......

Friday 18 September 2015

Topics Covered in Static Timing Analysis (STA)

Statistical static timing analysis

Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.

Limits of conventional STA

STA, while very successful, has a number of limitations:
  • Cannot easily handle within-die correlation, especially if spatial correlation is included.
  • Needs many corners to handle all possible cases.
  • If there are significant random variations, then in order to be conservative at all times, it is too pessimistic to result in competitive products.
  • Changes to address various correlation problems, such as CPPR (Common Path Pessimism Removal) make the basic algorithm slower than linear time, or non-incremental, or both.
SSTA attacks these limitations more or less directly. First, SSTA uses sensitivities to find correlations among delays. Then it uses these correlations when computing how to add statistical distributions of delays.
Interestingly, there is no technical reason why determistic STA could not be enhanced to handle correlation and sensitivities, by keeping a vector of sensitivities with each value as SSTA does. Historically, this seemed like a big burden to add to STA, whereas it was clear it was needed for SSTA, so no-one complained. See some of the criticism of SSTA below where this alternative is proposed.

Methods of SSTA

There are two main categories of SSTA algorithms - path-based and block-based methods.
A path-based algorithm[1] sums gate and wire delays on specific paths. The statistical calculation is simple, but the paths of interest must be identified prior to running the analysis. There is the potential that some other paths may be relevant but not analyzed so path selection is important.
A block-based algorithm[2] generates the arrival times (and required) times for each node, working forward (and backward) from the clocked elements. The advantage is completeness, and no need for path selection. The biggest problem is that a statistical max (or min) operation that also considered correlation is needed, which is a hard technical problem.
There are SSTA cell characterization tools that are now available such as Altos Design Automation's Variety tool.