Saturday, 31 December 2016

Tuesday, 27 December 2016

Physical design Interview Questions Part 6

Below are interview questions asked by one of the product based company

1. Have you ever worked on on lower nodes, like 14nm or 10nm?
2. what is difference between bulk MOS and FINFET?
3. How conduction takes place in MOS and FINFET transistors?
4. Is Antennae violation is functional failure or Manufacturing error? how can you fix antennae               violation
5. What is short circuit current, and how will you overcome this problem?
6. What is difference between static IR drop and dynamic IR drop?
7. On what all parameters does IR drop and Dynamic IR drop depends on?
8. Have you worked on Physical Verification?
9. What is soft checks in Physical verification?
10. How soft checks different from ERC?
11. What is difference between ERC and PERC?
12. What all the Physical verification test you perform during each stage of Physical design?
13. what XOR checks will do?
14. have you ever worked in STA?
15. have you involved in top level timing or your role limited to block level timing?

16. How OCV (onchip variation diffrent from ) AOCV (advance on chip variation)?
17 what is difference between  AOCV and POCV?
18 how timing related with PTC (postive temperature coefficient) and NTC (negative              temperature coefficient)
19 how derates varies in ocv, aocv and pocv?
20. what all parameter of uncertainty value in STA depends upon pre cts and post cts 

Tuesday, 1 November 2016

Flip Flop Vs Latch

Flip-flop
Latch
A flip-flop samples the inputs only at a clock event (rising edge, etc.)
A Latch samples the inputs continuously whenever it is enabled, that is, only when the enable signal is on. (or otherwise, it would be a wire, not a latch).
Flip-Flop are edge sensitive.
Latches are level sensitive.
Flipflop is sensitive to signal change and not on level. They can transfer data only at the single instant and data cannot be changed until next signal change.
Latch is sensitive to duration of pulse and can send or receive the data when the switch is on.
A flip-flop continuously checks its inputs and correspondingly changes its output only at times determined by clocking signal.
Latch is a device which continuously checks all its input and correspondingly changes its output, independent of the time determined by clocking signal.
It work’s on the basis of clock pulses.
It is based on enable function input
It is a edge trigerred , it mean that the output and the next state input changes when there is a change in clock pulse whether it may a +ve or -ve clock pulse.
It is a level trigerred , it mean that the output of present state and input of the next state depends on the level that is binary input 1 or 0.

Saturday, 19 March 2016

STA Interview Questions Part 4


  1. What is slack? 
  2. What is SDC constraint file contains? 
  3. Delay of a cell depends on which factors ? 
  4. Write Setup and Hold equations? 
  5. Where do you get the WLM's? Do you create WLM's? How do you specify? 
  6. In which case inserting a buffer will solve the setup timing? 
  7. What is cross talk? How it affects timing.
  8. How can you avoid cross talk? 
  9. How does shielding avoids Xtalk problem?
  10. Explain how more space helps in reducing Xtalk ?
  11. How buffer can be used in victim to avoid crosstalk? 
  12. What are the problems faced related to timing? 
  13. How did you resolve the setup and hold problem? 
  14. How delays vary with different PVT conditions? Show the graph. 
  15. What is cell delay and net delay? 
  16. What are delay models and what is the difference between them? 
  17. What is cloning and buffering? 
  18. What is the derate value that can be used? 
  19. What are  corner and mode  you checked  timing during sign-off? have you kept same dearte values for all corners and mode or you have changed? 
  20. What all the factors on which derating value depends? 
  21. What factors decides the setup time of flip-flop? 
  22. What is metastability? 
  23. Do slowing down the frequency help in fixing hold time violation? 
  24. slowing down the clock frequency helps in fixing setup time violations? 
  25. Timing analysis and correlation b/w PnR and signoff?
  26. Explain the concept of false path?
  27. What are multi-cycle paths? Give example. 
  28. How operating voltage can be used to satisfy timing? 
  29. please suggest some method to overcome setup time and Hold time violations?
  30. What is the difference between local-skew, global-skew and useful-skew? 
  31. What are factor does delay depends? How net delay and gate delay contribute to delay
  32. What are delay models and difference between them?
  33. What does SDC constraints has?
  34. What is wire load model? 
  35. Hold time does not depend on clock. Is it true? If so why? 
  36. What are the various timing-paths which should be taken care in STA?  
  37. What are setup and hold time violations? How can they be eliminated? 
  38. What is  virtual clock why it is required to define it? 
  39. What are the limitations in increasing the power supply to reduce delay? 
  40. How to resolve max-trans & max-cap?
  41. What is fixed first max-trans, max-cap OR setup,hold?
  42. What is OCV , why do we need?
  43. What is the difference b/w OCV and PVT.
  44. Why do we have timing exceptions?
  45. What is path based and graph based analysis?
  46. What should we do if we want to include analog macro in the extraction?
  47. Type of techniques around periphery of block to maintain timing.
  48. Techniques to minimize number of hold buffers.
  49. What point in design, we look at hold timing?
  50. Were design blocks multimode?
  51. Single set or multiple set of constraints (for clock)
  52. Any experience in timing closure/ECO?
  53. What format did you get your ECO file?  In Tcl script format or Graphical based format?
  54. Who set up primetime tool for design (like setting constraints)?
  55. For STA, do you need to create constraints for different operating modes like system mode or test mode?
  56. Techniques for I/O interface timing closure.
  57. Experience with Multimode/Single mode and multi corner blocks?
  58. Did top level person provide Tcl scripts?
  59. PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
  60. DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
  61. Have you done crosstalk analysis in your design?
  62. If you have undriven flops during check timing report, how will you proceed?
  63. If you have timing violations from a memory where the logic count is proper and 
  64. constraints are also validated, how do you solve this?
  65. How do you fix Noise violation? 
  66. How does upsizing of driver of victim help to fix noise violation?

Questions Related to Clock Tree Synthesis


  1. What is the goal of CTS? 
  2. What are clock trees? 
  3. What are clock tree types? 
  4. How many clocks were there in this project? 
  5. How will you use to take care  of all clocks used in your project?
  6. Are they come from seperate external resources or PLL? 
  7. How will you synthesize clock tree? 
  8. Why double spacing and multiple vias are used related to clock? 
  9. In which layer do you prefer for clock routing and why? 
  10. What is latency? Give the types? 
  11. Is it possible to have a zero skew in the design?
  12. What are the difference between High Fanout synthesis and Clock tree synthesis?
  13. Why CTS not done in synthesis?
  14. why we prefer  clock buffer during cts, how they are different with normal buffer?
  15. what is the target clock skew, clock latency target in your project?
  16. Does the design have a PLL? How many clocks generated from PLL.
  17. Are there derived clocks or complex clock generation circuitry? 
  18. what do you mean by gated clocks, how many gated clocks were there in your project?
  19. Is the clock gate used for timing or power? 
  20. Available cells for clock tree?
  21. Are there any special clock repeaters in the library? 
  22. Are there any EM, slew or capacitance limits on these repeaters? 
  23. Will the clock tree be shielded? If so, what are the shielding requirements? 
  24. why buffers having balanced rise and fall delays are preferred in CTS 
  25. Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
  26. Explain the concept clock domains crossing, how will you synchronize clock in that case?
  27. What is useful-skew mean? 
  28. What is skew, how will you minimize it, if you dont minimize what all problem you can face because of it? 
  29. Any special clock planning for block.
  30. How do you account for clock tree insertion for scan?
  31. Any clock generation block?
  32. Have you used shielding rules for clock nets in your design?
  33. How did you performed CTS for your block? How will you fix the clock latency violations?

Questions Related to Power Planning, IR drop and Low power


  1.  what is powerplanning, How you use to do i. Power estimation ii. power pads estimation (core & IO) iii. core ring width calculation iv. EMIR v. SSO 
  2.  What are preroutes in your design? 
  3.  How to power route multiVDD design?
  4. Power domains, partitioning, power routing for multi domains, placement of power switches?
  5. What are the various views of a macro or a cell?
  6.  What is the macro placement guidelines?
  7.  What all checks will you perform after Floor planning?
  8.  What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
  9. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
  10. How did you define your power structure for full chip? 
  11. How will you start power planning for your design?                                                                                                                                                                                                                      EMIR & low power:
  12. How power is related with clock frequency? 
  13. Can we achieve lower power with more than one voltage supply?
  14. Different low power techniques?
  15. methods of leakage reduction? 
  16. What are the vectors of dynamic power? 
  17. How can you reduce dynamic power? 
  18. If you have both IR drop and congestion how will you fix it? 
  19. Is increasing power line width and providing more number of straps are the only 
  20. solution to IR drop? 
  21. Why higher metal layers are preferred for Vdd and Vss? 
  22. What is IR drop? How it affects timing? 
  23. What is EM and it effects? how to resolve EM?
  24. Techniques to avoid IR problems? Dynamic & Static
  25. Do we have inactive blocks that we can shut off to reduce leakage power?
  26. What are Retention registers?
  27. Give the various techniques you know to minimize power consumption for CMOS logic? 
  28. Give the expression for CMOS switching power dissipation? 
  29. List out the factors affecting power consumption on a chip? 
  30. Any custom routes of analog/power? What were the requirements of custom routes?
  31. Any experience in low power techniques?
  32. Any experience with multi Vt libraries?
  33. What is total Static & dynamic power consumption in your design?

Wednesday, 16 March 2016

Physical Design Interview Question With Answers Part 2

Q.1 what are the other solution other than  increasing power line width and providing more number of straps to IR drop? 

Ans  below are some of the solution to IR drop problem
        Spreading the macros 
        Spreading standard cells 
        Usage of suitable blockage 


Q.2 Which is suitable place to insert buffer, in order to fix setup violation in reg to reg path? Is it near to launch or setup flop, Justify your answer?? 
Ans:- Buffer insertion is one of the method to overcome setup violation, Other methods are sizing of cells, Minimizing the data path etc. Lets assume that only  insertion of  buffer will solve the problem, then insert them Near to capture flop, Because there could be a chance other paths may be  passing  or originating from the launch flop. In that case  buffer insertion may could hamper others paths of launch flipflop. there is a chance it will improve all those paths or degrade. If all  paths have violation in launch flop also, then we can insert buffer near to launch flop. It could improve slack.

Q.3 How do you decide  best floorplan? 


Q.4 What are the challenges in the project?
Ans - Above answer you need to give according to your project common challenges could be  power planning- because of lots of IR drop  issue

      -could be  power target-because  more dynamic and leakage power 
      -It could be floorplanning issues in placing  macro.  
      - It could be CTS and CTO, because there may be chance you have to handle lots of clocks and clock domain crossing (CDC)
      -you might be facing challenges in timing fixtures
      -you might be facing library preparation, you may need to find some inconsistency in libraries. 


Q.5 )How will you synthesize clock tree? 
-Single clock-normal synthesis and optimization 
-Multiple clocks-Synthesis each clock separately 
-Multiple clocks with domain crossing-Synthesis each clock separately and balance the skew 

Q.6)How many clocks were there in this project
-It is specific to your project ,More number of the clocks more challenges you will face.

Q.7) How will you take care of all clocks? 
Ans -Multiple clocks --> synthesize separately --> skew Balancing-->optimization of clock tree 

Q.8) Are they come from separate external resources or Phase locked loop (PLL)? 
 -If it is from separate clock sources then balancing skew between these clock sources becomes challenging. 
-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy. 

Q.9)Why buffers are used in clock tree? 
 To balance skew (i.e. flop to flop delay) 
set_false_path Versus set_disable_timing in PrimeTime SI Crosstalk Analysis
set_false_path will prevent timing analysis from being performed on a path or paths. 
set_disable_timing will break the timing arc along a path or paths. With regards to 
crosstalk analysis, when an arc is broken with set_disable_timing edges will not 
physically propagate forward and will not cause downstream aggression. This could lead 
to optimistic crosstalk analysis. If there is a true edge that should be propagated for 
cross talk analysis and you only want to suppress the timing analysis of the path, then it is 
recommended to use set_false_path rather than set_disable_timing. If the edge cannot truly propagate past a point then set_disable_timing can be used to disable the path

Q.10)What is cross talk? 
Switching of the signal in one net can interfere neighboring net due to cross coupling 
capacitance.This affect is known as  Xtalk. Cross talk may lead setup or hold violation. 

Q.11) How can you avoid cross talk? 
-Double spacing, It means less capacitance, which ultimately results in less cross talk 
 -Multiple vias, which means less resistance and ultimately less RC delay 
 -Shielding,  which provide constant cross coupling capacitance
 -Buffer insertion can give strength the victim strength 

Q.12) How shielding avoids cross talk problem? What exactly happens there? 
-Crosstalk noise which is coupled to ground VSS (or power (VDD)) since shielding of  layers are 

connected to either power or ground

Sunday, 28 February 2016

Physical Design (VLSI) Interview Questions Links

  • Physical Design interview Questions

  1. Physical Design interview Questions With Answers P...
  2. Physical Design Interview Question With Answers Part 2
  3. Physical Design Interview Question Part 1
  4. Physical Design Interview Question Part 2
  5. Physical Design Interview Question Part 3
  6. Physical Design (Floorplanning) interview Question...
  7. Physical Design (Power planning) Interview Questio...
  8. Frequently Asked Question in Physical Design Inter...
  9. Frequently Asked Question Part 2
  10. Questions Related to Power Planning, IR drop and Low power
  11. Questions Related to Clock Tree Synthesis
  12. Physical Design Interview Question Part 6


        STA Interview Question

Physical Design (Power planning) Interview Question Part 5


  1. . How will you do power planning? 
  2.  Power estimation
  3.  power pads estimation (core & IO) 
  4. core ring width calculation
  5. EMIR considerations
  6. SSO considerations
  7. What are preroutes in your design? 
  8. How to power route multiVDD design?
  9.  Power domains, partitioning, power routing for multi domains, placement of power switches?
  10.  What are the various views of a macro or a cell?
  11.  What is the macro placement guidelines?
  12. What all checks will you perform after Floor planning?
  13. What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
  14. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
  15. How did you define your power structure for full chip? 
  16. How will you start power planning for your design?
  17. EMIR & low power:
  18. How power is related with clock frequency? 
  19. Can we achieve lower power with more than one voltage supply?
  20. Different low power techniques?
  21. methods of leakage reduction? 
  22. What are the vectors of dynamic power? 
  23. How can you reduce dynamic power? 
  24. If you have both IR drop and congestion how will you fix it? 
  25. Is increasing power line width and providing more number of straps are the only solution to IR drop? 
  26. Why higher metal layers are preferred for Vdd and Vss? 
  27. What is IR drop? How it affects timing? 
  28. What is EM and it effects? how to resolve EM?
  29. Techniques to avoid IR problems? Dynamic & Static
  30. Do we have inactive blocks that we can shut off to reduce leakage power?
  31. What are Retention registers?
  32. Do we have blocks that can run at slower rate in certain modes? Can we reduce the 
  33. voltage during those modes?
  34. Give the various techniques you know to minimize power consumption for CMOS logic? 
  35. Give the expression for CMOS switching power dissipation? 
  36. List out the factors affecting power consumption on a chip? 
  37. Any custom routes of analog/power? What were the requirements of custom routes?
  38. Any experience in low power techniques?
  39. Any experience with multi Vt libraries?
  40. What is total Static & dynamic power consumption in your design?

Physical Design (Floorplanning) interview Question Part 4

1. Die size estimation:

2. How will you decide best floorplan? 

3. how to decide Aspect ratio? 

4.how to decide Macro placement ?

5. What is the target die size?

6.What is the expected utilization?

7. Does the area estimate include power/signal routing? 

8.What gates/mm2 has been assumed?

9.how to decide no. of routing layers?

10. Any special power routing requirements?

12. Please draw the overall floorplan ?

13. Is there an existing floorplan available in DEF? 

14. What are the number and type of macros (memory, PLL, etc.)?

15. Are there any analog blocks in the design? 

16. Placement of PLL? Analog placement requirements

17. Did you receive block size, pin locations from top level person?

18. How will you do floorplanning?(with out having data flow details)

19. How would you go about floorplanning when you have lots(hundreds) of macros?

20. What are the general guidelines to be followed when doing floorplanning?

21. how to decide Full chip IO ring: 

22. how to decide Total number of pins/pads and Location? 

23. how to decide Is the design pad limited? 

24. Number of digital I/O pins/pads?

25. Number of analog signal pins/pads? 

26. Number of power/ground pins/pads?

27. Will this chip use a wire bond/flipchip package? 

28. How IOSSO taken care? 

29. What ESD protection used for the IO ring? 

30. If flipchip, is it I/O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide?

Physical Design Interview Question Part 3

1. How many blocks/chips designed in your total years of Experience?

2. What is the latest project you finished? Was it block level implementation or full-chip implementation?

3. What is the design application?

4. Input is RTL or gate level netlist?

5. Explain Netlist(or RTL)-gdsii flow?

6. What are the input needs for your design? 

7. In which field are you interested? 

8. What is the most challenging task you handled? 

9. What are the challenges you faced in P&R flow? 

10. What parameters (or aspects) differentiate Chip Design and Block level design? 

12. Differentiate between a Hierarchical Design and flat design? 

13. What is the difference between soft macro and hard macro?

14. What are Ips?

15. What are the challenges you will see in lower technology?

16. What scan techniques being used?

17. Experience with timing closure & congestion issues?

18. Any experience with ECO (functional or timing ECO).

19. Towards the end of the project, what are some of the issues that can pop up , and 

20. how can they be fixed?

21. If you have shifted from one tool to another one, how long did it take to ramp up 

on the new tool?

22. What is the difference between a latch and a flip-flop?

23. On what basis we decide the clock frequency in any design?

24. Define threshold voltage? 

25. How does the size PMOS & NMOS transistors increases the threshold voltage? 

26.What is the effect of temperature on threshold voltage? 

27.What is the effect of gate voltage on mobility? 

28. What is the effect of temperature on mobility? 

29. If  we invert o/p of D flip-flop in the ip how does it will behave?

30.Design a circuit to divide input frequency by 2?

31. What is the maximum drive strength of standard buffers and inverters are available in your design? 

32. Why we increase the size and strength of inverters in buffer design? What will happen if you user inverter or buffer of maximum strength and size? 

33. What does lef and lib file contains?

34. What is generally in the x axis and y axis and what is linear line in any library(NLDM)?

35. What are the high speed and low speed cells?


36. What is the exact meaning of a capacitance?

Saturday, 20 February 2016

STA Interview Question Part 3


  1. What should we do if we want to include analog macro in the extraction?
  2. Type of techniques around periphery of block to maintain timing.
  3. Techniques to minimize number of hold buffers.
  4. What point in design, we look at hold timing?
  5. Were design blocks multimode?
  6. Single set or multiple set of constraints (for clock)
  7. Any experience in timing closure/ECO?
  8. What format did you get your ECO file?  In Tcl script format or Graphical based format?
  9. Who set up primetime tool for design (like setting constraints)?
  10. For STA, do you need to create constraints for different operating modes like system mode or test mode?
  11. Techniques for I/O interface timing closure.
  12. Experience with Multimode/Single mode and multi corner blocks?
  13. Did top level person provide Tcl scripts?
  14. PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
  15. DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
  16. Have you done crosstalk analysis in your design?
  17. If you have undriven flops during check timing report, how will you proceed?
  18. If you have timing violations from a memory where the logic count is proper and constraints are also validated, how do you solve this?
  19. How do you fix Noise violation? 
  20. How does upsizing of driver of victim help to fix noise violation?

STA Interview Questions Part 2

  1. Timing analysis and correlation b/w PnR and signoff?
  2. What do you mean by false path? Explain with an example? 
  3. Explain the concept of multi-cycle paths with PT command? 
  4. How operating voltage can be used to satisfy timing? 
  5. How to solve setup time and Hold time violations in the design?
  6. What is the difference between local-skew & global-skew? 
  7. What do you mean by useful skew, what is the advantage of it?
  8. What is cell delay and net delay? 
  9. What are delay models and difference between them?
  10. What does SDC constraints has?
  11. What is wire load model? 
  12. Hold time does not depend on clock. Is it true? If so why? 
  13. What do you mean by timing-paths? what are the timing path need to be taken care in STA?  
  14. What do you mean by setup violation and hold time violations? How can they be eliminated? 
  15. What is meant by virtual clock definition and why do i need it? 
  16. how does  increasing the power supply to reduce delay? 
  17. How to resolve max-trans & max-cap?
  18. What is fixed first max-trans, max-cap OR setup,hold?
  19. What is OCV , why do we need?
  20. What is the difference b/w OCV and PVT.
  21. Why do we have timing exceptions?
  22. What is path based and graph based analysis?


STA Interview Questions Part 1

What is slack?

What is SDC constraint file contains?

Delay of a cell depends on which factors ?

Write Setup and Hold equations?

Where do you get the WLM's? Do you create WLM's? How do you specify?

In which case inserting a buffer will solve the setup timing?

What is cross talk? How it affects timing.

How can you avoid cross talk?

what is  shielding ? how doe it prevents  cross talk ?

How spacing helps in reducing crosstalk noise?

How buffer can be used in victim to avoid crosstalk?

What are the problems faced related to timing?

How did you resolve the setup and hold problem?

How does delays varies with different PVT conditions? please explain with the help of graph.

What is cell delay and net delay?

What are different delay models  available and what are the difference between them?

What is cloning and buffering?

What is the derate value that can be used?

What are the corners you check for timing sign-off? Is there any changes in the derate value for each corner?

Where do you mean by the de-rating value? What are the factors that decide the de-rating values?

factor?

What factors decides the setup time of flip-flop?

What is metastability?

In a system with insufficient hold time, will slowing down the clock frequency help?

Physical Design Interview Question Part 2


  1. How many blocks/chips designed in your total years of Experience?
  2. What is the latest project you finished? Was it block/full-chip?
  3. What is the design application?
  4. Input is RTL or gate level netlist?
  5. Explain Netlist(or RTL)-gdsii flow?
  6. What are the input needs for your design? 
  7. In which field are you interested? 
  8. What is the most challenging task you handled? 
  9. What is the most challenging job in P&R flow?
  10. What parameters (or aspects) differentiate Chip Design and Block level design? 
  11. List down difference between a flat and hierarchical design? 
  12. What is the difference between soft macro and hard macro?
  13. What are the challenges seen as technology shrinks?
  14. What scan techniques being used?
  15. Experience with timing closure & congestion issues?
  16. Any experience with ECO (functional or timing ECO).
  17. what are issues you face during tapeout time?
  18. If you have shifted from one tool to another one, how long did it take to ramp up 
  19. on the new tool?
  20. What is the difference between a latch and a flip-flop?
  21. what all the parameters on which clock frequency depends in design?
  22. Define threshold voltage? 
  23. How do you size NMOS and PMOS transistors to increase the threshold voltage? 
  24. how threshold voltage is dependent on temperature? 
  25. What is the effect of gate voltage on mobility? 
  26. What is the effect of temperature on mobility? 
  27. Design a circuit to divide input frequency by 2?

Physical Design Interview Question Part 1


  1. Explain concept of   cross talk? 
  2. How can you overcome cross talk problem? 
  3. what is shielding? how it avoid avoids crosstalk problem? 
  4. how spacing h reducing crosstalk noise? 
  5. Why double spacing and multiple vias are used related to clock? 
  6. where do you insert buffer to avoid crosstalk? how buffer insertion solve the problem?
  7. Difference between Chip Design and Block level design? 
  8. What are the ways to place macros in a full chip design? 
  9. what are the differences between Hierarchical Design and flat design? 
  10. Why 500 MHz clock design is complex than 48Mhz design? 
  11. What all tools used in physical verification? 
  12. what are the inputs you will give in physical verification
  13. how will you solve the congestion between two macros? 
  14. what all parameters you will consider while estimating die size? 
  15. What is each macro size and number of standard cell count? 
  16. Depends on your design. 
  17. What are the input needs for your design?  
  18. What does SDC (Synopsys design contraint)  file contains? 
  19. how will give Clock definitions ?
  20. what are timing Timing exception, how will you constraint them?
  21. what is Input and Output delays, what are prime time  commands for it?
  22. How did you do power planning? 
  23. Explain, how will you find number of power pad and IO power pads? 
  24. How the  number of power straps calculate? 
  25. How to find total power of chip, What are the problems you can  faced with respect to timing? 
  26. what is  setup and hold problem, how will you solve it?
  27. which is preferable layer for clock routing and why? 
  28. what do you mean by IR drop problem, how will you overcome by this problem? 
  29. what is  antenna effect, how does it impact the and how would you resolve antennae effect problem? 
  30. How are the PVT conditions? Describe using graph?
  31. Describe the physical design flow?
  32. what all the  and inputs and outputs for each step of physical design? 
  33. What is cell delay and net delay, how will you reduce this delays? 
  34. What are  the different timing delay models available? 
  35. What is wire load model (WLM)?  
  36. Why higher metal layers are preferred for power? 
  37. What do you mean by logic optimization techniques, how it will work?
  38. what is slack, how will you calculate slack?
  39. what are the parameters on which slack depends on?
  40. What do you mean by of negative slack, how will u make it positive?  
  41. What is EM and it effects? 
  42. What are types of routing ?  
  43. What do you mean by clock latency? what are the  types of clock latecies? 
  44. What is track assignment in routing stage? 


Sunday, 14 February 2016

Physical Design interview Questions With Answers Part 1

Q.1) In what all area of physical design you have worked on?

Ans) Answer to this question depends expertise and to the requirement for

which you have been interviewed.


Q.2) what all low power techniques, you have used? How low power and latest

technologies are related?


Q.3) what input vector control  leakage reduction method?

Ans) Leakage current of a gate is also input dependent. Hence, we need to find the set of inputs

which gives least leakage. By applying this minimum leakage vector decreases the leakage current of the circuit  in  standby mode.


This method also called input vector controlled method of leakage reduction.


Q.4)How can you reduce dynamic power?

Ans) -Reduce switching activity by designing good RTL

 -Clock gating

 -Architectural improvements

 -Reduce supply voltage

 -Use multiple voltage domains-Multi vdd


Q.5)What are the vectors of dynamic power?

Ans) Voltage and Current

Q.6)How will you Computes a target IR drop value in the core from the target IR drop value?

Ans) Target IR drop in the core = <target IR drop from the package-to-I/O-to-core> –<IR drop

from package to core boundary>

(IR drop from package to core boundary = <IR drop in package> + <IR drop in bonding

wires> + <IR drop at I/O cells>)・IR drop is calculated by the unit of Power Domain for

multi power voltages.

Thursday, 21 January 2016

FAQ in Low Power


  1. What are retention flops, where they are used?
  2. what are isolation cells? where they are placed and why isolation's cells are used?
  3. what is level shifter? what is use of level shifters?, where you will place them?
  4. what is clock gating ?
  5. what is power gating ?
  6. what is MTCMOS switch, how will you place them?
  7. what is UPF/CPF file, what kind of information it contain?
  8. Difference between always ON and switchable domain?

Friday, 15 January 2016

IP in Vlsi

An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse , IP cores are part of the growing electronic design automation ( EDA ) industry trend towards repeated use of previously designed components. Ideally, an IP core should be entirely portable - that is, able to easily be inserted into any vendor technology or design methodology. Universal Asynchronous Receiver/Transmitter ( UART s), central processing units ( CPU s), Ethernet controllers, andPCI interfaces are all examples of IP cores.
IP cores fall into one of three categories: hard cores , firm cores , or soft cores . Hard cores are physical manifestations of the IP design. These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gate s and associated interconnections making up an integrated circuit ) or hardware description language ( HDL ) code.
A number of organizations, such as the Free IP Project and Open Cores, have formed to promote open sharing of IP cores.

Wednesday, 13 January 2016

What is capacitive loading? How does it affect slew rate?

By definition slew rate of a circuit is rate at which a circuit can charge and dischare 

capacitance. This capacitance may be external capacitor CL or  Cg gate 

capacitances of transistors connected to this circuit.  



Normally a digital circuit during switching must charge or discharge  CL or Cg at 

faster rate, and this charging rate depends on output current of the circuit.  



capacitive loading occurs when this output current is insufficient to drive load 

capacitances CL and one or more gates connected to original circuit as a result slew 

rate of the circuit decreases and circuit becomes slow(takes more time to charge 

capacitors connected to circuit).

Advantage and Disadvantage of using Asynchronous Reset

Advantages of using asynchronous reset


 Implementation of asynchronous reset requires less number of gates compared to 

synchronous reset design.

 Asynchronous reset is fast.

 Clocking scheme is not necessary for an asynchronous design. Hence design 

consumes less power. Asynchronous design style is also one of the latest design 

options to achieve low power. Design community is scrathing their head over 

asynchronous design possibilities.

 Disadvantages of using asynchronous reset 


 Metastability problems are main concerns of asynchronous reset scheme (design). 

 Static timing analysis and DFT becomes difficult due to asynchronous reset.

Sunday, 10 January 2016

Manufacture of SOI wafers

SiO2-based SOI wafers can be produced by several methods:
  • SIMOX - Separation by IMplantation of OXygen – uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2layer.
  • Wafer bonding – the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
    • One prominent example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
    • NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.
    • ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.
  • Seed methods- wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.


References

1.https://en.wikipedia.org/wiki/Silicon_on_insulator#/media/File:Smart_Cut_SOI_Wafer_Manufacturing_Schema.svg
2. https://en.wikipedia.org/wiki/Silicon_on_insulator

Industrial Need of SOI

 Industrial Need of SOI


The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:
  • Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
  • Resistance to latchup due to complete isolation of the n- and p-well structures.
  • Higher performance at equivalent VDD. Can work at low VDD's.
  • Reduced temperature dependency due to no doping.
  • Better yield due to high density, better wafer utilization.
  • Reduced antenna issues
  • No body or well taps are needed.
  • Lower leakage currents due to isolation thus higher power efficiency.
  • Inherently radiation hardened ( resistant to soft errors ), thus reducing the need for redundancy.
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.


References

1. https://en.wikipedia.org/wiki/Silicon_on_insulator

Silicon on Insulator

Introduction

Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.


References
1. https://en.wikipedia.org/wiki/Silicon_on_insulator#/media/File:SIMOX_processing_schematic.svg
2. https://en.wikipedia.org/wiki/Silicon_on_insulator



FinFET

finFET seems to be the most promising and disruptive technology at the moment able to mantain the Moore’s Law trend and expectations. The most active players (IDM, Foundries, EDA companies and IP providers) in the semiconductor market are putting a lot of effort, investments and emphasis on this hot topic.
For this reason I decided to collect information and share a post regarding this technology. It’s not anymore the time for me to enter in mathematical and physical details, but my interest  is to understand the reasons and the advantages of the FinFET technology from a marketing perspective.

Reasons

The Moore’s Law and the market are pushing constantly to increase the density of transistors in chip and the performances in term of speed and power consumption. This scaling process seems to be at a technology limit for the planar transistor with length below 20nm: the electrical parameters start degrading and the silicon process variations impact heavily in the performances. The main reason of this degradation is due to the planar structure itself: the gate does not have a good electrostatic field control away from the surface of the channel. With geometry scaling,  it brings to:
  • Lower current in the channel
  • Leakage current drain-source when the transistor is theoretically switched off 
  • Short channel effect
  • High dependence on process variations (Vth and swing).

Solution



The solution seems to be indeed the 3D approach:  the channel between source and drain is built as a three-dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped around the channel, so the gate can control the channel electrical field. In this structure, the gate can control much better the electrical field in the 3D channel.

Several options and enhancement are proposed. In the picture below a finFET has been built on SOI with a further reduction of current leakage. There can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.

Advantages


FinFET technology impacts all the electrical parameters of the transistor and you have benefit in power consumption (static and dynamic), speed and voltage supply range. FinFETs also improve the always challenging tradeoff between performance and power: you can go faster with the same amount of power, compared to the planar equivalent, or save power at the same speed. In a list, the promised advantages over plan transistor:
  • Higher drain current
  • up to 37% switching speed
  • Lower switching voltage
  • less than half the dynamic power
  • 90% less static leakage current
The above points reached with a low cost impact: leading foundries estimate the additional processing cost of 3D devices to be 2% to 5% higher than that of the corresponding Planar wafer fabrication.

State of the Art


Almost all the big players in the semiconductor eco-system are focusing on the finFET technology, so news, announcements and updates come out every day.
The finFET era started  in 2011, when Intel unveiled the newfangled transistor technology at the 22nm node (now in production)Intel plans are to ramp up its second-generation finFET devices at 14nm by year’s end and move to 11nm by 2015.
Silicon Foundries are already defining their plans with finFETs technology. GlobalFoundries will deliver14nm finFET by 2014 and 10nm finFet by 2015. TSMC is planning to deliver 16nm finFET by 2014.
EDA player are dedicating big effort to model this complex device and to deliver compelling design tools to designers. In particular Synopsys is working hard to deliver tools and IP for FinFET design, as in the news.


Conclusion

Maybe we are at the beginning of a new era. finFETs can potentially determinate a big step forward in the never ending effort to reduce power consumption, to increase switching speed and number of transistors. Always with a cost reduction.

Refrerences

1. https://en.m.wikipedia.org/wiki/FinFET#FINFET
2. https://cologneseandrea.wordpress.com/2013/03/20/finfet-technology-for-dummies-like-me/