Saturday 20 February 2016

STA Interview Question Part 3

  1. What should we do if we want to include analog macro in the extraction?
  2. Type of techniques around periphery of block to maintain timing.
  3. Techniques to minimize number of hold buffers.
  4. What point in design, we look at hold timing?
  5. Were design blocks multimode?
  6. Single set or multiple set of constraints (for clock)
  7. Any experience in timing closure/ECO?
  8. What format did you get your ECO file?  In Tcl script format or Graphical based format?
  9. Who set up primetime tool for design (like setting constraints)?
  10. For STA, do you need to create constraints for different operating modes like system mode or test mode?
  11. Techniques for I/O interface timing closure.
  12. Experience with Multimode/Single mode and multi corner blocks?
  13. Did top level person provide Tcl scripts?
  14. PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
  15. DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
  16. Have you done crosstalk analysis in your design?
  17. If you have undriven flops during check timing report, how will you proceed?
  18. If you have timing violations from a memory where the logic count is proper and constraints are also validated, how do you solve this?
  19. How do you fix Noise violation? 
  20. How does upsizing of driver of victim help to fix noise violation?

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