Routing

Routing Concept In Physical Design

After the floorplanning and placement steps in the design, routing needs to be done. Routing is nothing but connecting the various blocks in the chip with one another. Until now, the blocks were only just placed on the chip. Routing also is spilt into two steps

1. Global Routing:

It basically plans the overall connections between all the blocks and the nets. Its main aim is to minimize the total interconnect length, minimize the critical path delay. It determines the track assignments for each interconnect.

a. The chip is divided into small blocks. These small blocks are called routing bins. The size of the routing bin depends on the algorithm the tool uses. Each routing bin is also called a gcell. The size of this gcell depends on the tool.Each gcell has a finite number of horizontal and vertical tracks. Global routing assigns nets to specific gcells but it does not define the specific tracks for each of them. The global router connects two different gcells from the centre point of each gcell.

b. Track Assignment: The Global router keeps track of how many interconnections are going in each of direction. This is nothing but the routing demand. The number of routing layers that are available depend on the design and also, if the die size is more, the greater the routing tracks. Each routing layer has a minimum width spacing rule, and its own routing capacity. For Example: For a 5 metal layer design, if Metal 1, 4, 5 are partially up for inter-cell connections, pin, VDD, VSS connections, the only layers which are routable 100% are Metal2 and Metal3. So if the routing demand goes over the routing supply, it causes Congestion. Congestion leads to DRC errors and slow runtime

2. Detailed Routing:

In this step, the actual connection between all the nets takes place. It creates the actual via and metal connections. The main objective of detailed routing is to minimize the total area, wire length, delay in the critical paths. It specifies the specific tracks for the interconnection; each layer has its own routing grid, rules. During the final routing, the width, layer, and exact location of the interconnection are decided.After detailed routing is complete, the exact length and the position of each interconnect for every net in the design is known. The parasitic capacitance, resistance can now is extracted to determine the actual delays in the design. The parasitic extraction is done by extraction tools. This information is back annotated and the timing of the design is now calculated using the actual delays by the Static Timing Analysis Tool. After timing is met and all other verification is performed such as LVS, etc, the design is sent to the foundry to manufacture the chip.

Macro Placement Tips

The formula to calculate spacing between two macro is (width+spacing x number of pins /vertical routing layers) + spacing. It is better adding an additional spacing because you can avoid violation with the side of macros.

Tips for macro Placement /Floorplanning :

1. Place macros around chip periphery.
If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and perplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in the GUI.
3. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
4. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case estimating routing resources with precision is very important. Use the congestion map from trialRoute to identify hot spots between macros and adjust their placement as needed.
5. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.

Floor Planning

Introduction To Floor Planning

This is the first major step in getting your layout done, and this is the most important one.Your floorplan determines your chip quality. Floorplanning includes

1. Define the size of your chip/block and Aspect ratio
2. Defining the core area and IO core spacing
3. Defining ports specified by top level engineer.
4. Design a Floor Plan and Power Network with horizontal metal layer such that the total IR Drop must be less than 5% (VDD+VSS) of VDD to operate within the power budget.
5. IO Placement/Pin placement
6. Allocates power routing resources
7. Place the hard macros (fly-line analysis) and reserve space for standard cells. (Please refer rules for placing hard macros)
8. Defining Placement and Routing blockages blockages
9. If we have multi height cells in the reference library separate placement rows have to be provided for two different unit tiles.
10. Creating I/O Rings
11. Creating the Pad Ring for the Chip
12. Creating I/O Pin Rings for Blocks                                                                                                                                                                                                                                                                                                                                                                    Every subsequent stage like placement, routing and timing closure is dependent on how good your foorplan is. In a real time design, you go through many iterations before you arrive at an optimum floorplan.

Floorplanning takes in some of the geometrical constraints in a design. Examples of this are:

• Bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip.
• Line drivers often have to be located as close to bonding pads as possible.
• Chip area is therefore in some cases given a minimum area in order to fit in the required number of pads.
• Areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit.
• Purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks.
• Some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.

Inputs for Floor Planning Stage

1. Synthesized Netlist (.v, .vhdl)
2. Logical and Physical Libraries
3. TLU+ Files
4. Physical partitioning information of the design
5. Design Constrains (SDC)
6. Physical information of your design (rules for targeted technology)
7. Floorplan parameters like height, width, utilization, aspect ratio etc.
8. Pin/pad Position

Outputs of Floor Planning Stage

• Die/Block area
• I/O pad/placed
• Macro placed
• Power grid design
• Power pre-routing
• Standard cell placement areas.

Purpose of Floor Planning

   The first step in the Physical Design flow is Floor Planning. Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.

    Based on the area of the design and the hierarchy, a suitable floorplan is decided upon. Floor Planning takes into account the macro's used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Floor planning also decides the IO structure, aspect ratio of the design. A bad floor-plan will lead to waste-age of die area and routing congestion.

    In many design methodologies, Area and Speed are considered to be things that should be traded off against each other. The reason this is so is probably because there are limited routing resources, and the more routing resources that are used, the slower the design will operate. Optimizing for minimum area allows the design to use fewer resources, but also allows the sections of the design to be closer together. This leads to shorter interconnect distances, less routing resources to be used, faster end-to-end signal paths, and even faster and more consistent place and route times. Done correctly , there are no negatives to Floor-planning.
As a general rule, data-path sections benefit most from Floorplanning, and random logic, state machines, and other non-structured logic can safely be left to the placer section of the place and route software.

    Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. Example structures that make up data paths are Adders, Subtractors, Counters, Registers, and Muxes.


You may be also interested below topics

• Blockages
• Aspect Ratio
• Design Netlist
• Some Basic Rules For Placing Macros
• IO Placement / Pin placement
• Core Utilization
• Die Area calculation
• Design Exchange Format (DEF) Files
• Library Exchange Format (LEF) Files
• Macro Placement Tips
• Glue Logic
• 
  

What is follow pin in VLSI physical design?

 In VLSI physical design, a follow pin is a special type of pin used to specify the routing direction of a net or signal. The follow pin is used to guide the routing of a net, making sure that it follows a specific direction or path.

Follow pins are often used in high-speed digital circuits, where the routing of signals can significantly affect the performance of the circuit. Designers may ensure that the signal takes the best path by setting the routing direction of a net using a follow pin, lowering the chance of crosstalk and other problems. It often sits at the start or end of a net and specifies which way the signal should be sent. The signal is then routed along the designated path using the pins attached to the net, ensuring that it travels in the intended direction. To further boost the performance of the circuit, follow pins can be utilised in conjunction with other routing strategies like wire spacing and shielding. In summary, a follow pin is a special type of pin used in VLSI physical design to specify the routing direction of a net or signal. It is used to guide the routing of a net, ensuring that the signal follows the optimal path and reducing the risk of crosstalk and other issues. Follow pins are particularly useful in high-speed digital circuits, where signal routing can significantly affect circuit performance.

Frequently Asked Question Part 2

                                                                                                                           Previous Page

* What is signal integrity? How it affects Timing?
* What is IR drop? How to avoid IR drop .how it affects timing?
* What is EM and it effects?
* What is floor plan and power plan?
* What are types of routing?
* What is a grid .why we need and different types of grids?
* What is core and how u will decide w/h ratio for core?
* What is effective utilization and chip utilization?
* What is latency? Give the types?
* What is LEF?
* What is DEF?
* What are the steps involved in designing an optimal pad ring?
* What are the steps that you have done in the design flow?
* What are the issues in floor plan?
* How can you estimate area of block?
* How much aspect ratio should be kept (or have you kept) and what is the utilization?
* How to calculate core ring and stripe widths?
* What if hot spot found in some area of block? How you tackle this?
* After adding stripes also if you have hot spot what to do?
* What is threshold voltage? How it affect timing?
* What is content of lib, lef, sdc?
* What is meant my 9 track, 12 track standard cells?
* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
* What is setup and hold? Why there are ? What if setup violation fix and hold violation fixtures?
* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
* How R and C values are affecting time?
* How ohm (R), fared (C) is related to second (T)?
* What is transition? What if transition time is more?
* What is difference between normal buffer and clock buffer?
* What is antenna effect? How it is avoided?
* What is ESD?
* What is cross talk? How can you avoid?
* How double spacing will avoid cross talk?
* What is difference between HFN synthesis and CTS?
* What is hold problem? How can you avoid hold time violations?
* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
* What is partial floor plan?
* What parameters (or aspects) differentiate Chip Design & Block level design??
* How do you place macros in a full chip design?
* Differentiate between a Hierarchical Design and flat design?
* Which is more complicated when u have a 48 MHz and 500 MHz clock design?
* Name few tools which you used for physical verification?
* What are the input files will you give for primetime correlation?
* What are the algorithms used while routing? Will it optimize wire length?
* How will you decide the Pin location in block level design?
* If the routing congestion exists between two macros, then what will you do?
* How will you place the macros?
* How will you decide the die size?
* If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
* If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
* In your project what is die size, number of metal layers, technology, foundry, number of clocks?
* How many macros in your design?
* What is each macro size and no. of standard cell count?
* How did u handle the Clock in your design?
* What are the Input needs for your design?
* What is SDC constraint file contains?
* How did you do power planning?
* How to find total chip power?
* How to calculate core ring width, macro ring width and strap or trunk width?
* How to find number of power pad and IO power pads?
* What are the problems faced related to timing?
* How did u resolve the setup and hold problem?
* If in your design 10000 and more numbers of problems come, then what you will do?
* In which layer do you prefer for clock routing and why?
* If in your design has reset pin, then it’ll affect input pin or output pin or both?
* During power analysis, if you are facing IR drop problem, then how did u avoid?
* Define antenna problem and how did u resolve these problem?
* How delays vary with different PVT conditions? Show the graph.
* Explain the flow of physical design and inputs and outputs for each step in flow.
* What is cell delay and net delay?
* What are delay models and what is the difference between them?
* What is wire load model?
* What does SDC constraints has?
* Why higher metal layers are preferred for Vdd and Vss?
* What is logic optimization and give some methods of logic optimization.
* What is the significance of negative slack?
* How the width of metal and number of straps calculated for power and ground?
* What is negative slack ? How it affects timing?
* What is track assignment?
* What is grided and gridless routing?
* What is a macro and standard cell?
* What is congestion?
* Whether congestion is related to placement or routing?
* What are clock trees?
* What are clock tree types?
* Which layer is used for clock routing and why?
* What is cloning and buffering?
* What are placement blockages?
* How slow and fast transition at inputs effect timing for gates?
* What is antenna effect?
* What are DFM issues?
* What is .lib, LEF, DEF, .tf?
* What is the difference between synthesis and simulation?
* What is metal density, metal slotting rule?
* What is OPC, PSM?
* Why clock is not synthesized in DC?
* What are high-Vt and low-Vt cells?
* What corner cells contains?
* What is the difference between core filler cells and metal fillers?
* How to decide number of pads in chip level design?
* What is tie-high and tie-low cells and where it is used

Routing Grid

That generally call routing grid, to match the pin std cell position.

Historically, the backend designer should align this grid function of the std cell, now the tool are generally able to analyze the std cell pins positions.

The tool router has a routing grid, plus a sub-routing that is the forth of the routing grid to provide more routing possibility

Frequently Asked Question in Physical Design Interviews

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Questions                                                                                       Next Page

1. Tell me about your project experience?
2. What are technology node you worked on?
3. How Many Tape out you did? 
4. which customer/client you have worked with?

Questions Based on Floor Planning

1. What all checks you will perform before starting floor planning?
2. What are inputs given to the floor planning stage?
3. What kind of blockages you have given to your last project?
4. How you will determine the distance between two macros?
5. what is the size of your block?
6. what are general guidelines you followed for Macro placement?
7. How many macros and standard cell were there in your block?
8. how will you place macro?
9. In your design memories are there but not connected anywhere, where you will place the memory?
10. if your design is 8 layer and your block is 4 layer, how will you place.

Question Based on Placement and Route

1. How many blockages are there in your design, how will you solve blockages
2. whether routing is possible in HALO
3. How will you solve routing congestion
4. How many type of congestion were there in your design
5. How will you find the distance between two macros
6. how you use to do routing
7. How will you solve the congestion when utilization and cell density is more?

Question Based on STA & CTS

1. What is goal of CTS?
2. What are inputs to CTS?
3. What is the target skew?
4. what are inputs you have given in CTS
5. how will you solve setup violation
6. what is hold, how will you solve it
7. suppose your design is of 500 mhz frequency, setup and hold are fix. If frequency is increased to 750 mhz, what will happen to setup and hold
8. how will you build clock tree, describe the procedure
9. what is slew, what is relation between transition and slew
10. how you use to do cts
11. what is virtual clock
12. how will you save time in cts optimizations
13. what are false path
14. How signal integrity impact setup and hold violation?
15. How to fix setup and hold violation after p & r?

Question Based on Physical Verfication

1. what are the files getting evaluated during LVS stage

Miscellaneous Questions

 For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select and Why?
What is partial floor plan?  
 What are the steps that you have done in the design flow?What are the issues in floor plan?
How can you estimate area of block?
How much aspect ratio should be kept (or have you kept) a
what is the utilization?
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
 
After adding stripes also if you have hot spot what to do?
What is threshold voltage? How it affect timing?
What is content of lib, lef, sdc? 
What is meant by 9 track, 12 track standard cells?
What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
What is setup Time and hold time? Why there are ? What if setup Violates and hold violates?In a circuit, for reg to reg path ...
Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
How R and C values are affecting time?How ohm (R), fared (C) is related to second (T)?What is transition? 
What if transition time is more?
What is difference between normal buffer and clock buffer?
What is antenna effect?
 What is ESD?
What is cross talk? How can you avoid?
How double spacing will avoid cross talk?
What is difference between HFN synthesis and CTS?What is hold problem? How can you avoid it?
What are the steps that you have done in the design flow?What are the issues in floor plan?
How can you estimate area of block?How much aspect ratio should be kept (or have you kept) and 
what is the utilization?How to calculate core ring and stripe widths?What if hot spot found in some area of block? 
How you tackle this?After adding stripes also if you have hot spot what to do?What is threshold voltage? 
What are DFM issues? What is the difference between synthesis and simulation?What is metal density
 metal slotting rule?What is OPC, PSM?Why clock is not synthesized in DC?What are high-Vt and low-Vt cells?
What corner cells contains?What is the difference between core filler cells and metal fillers?
How to decide number of pads in chip level design?What is tie-high and tie-low cells and where it is used?
What is DEF?
What are the steps involved in designing an optimal pad ring?
What is grided and gridless routing?What is a macro and standard cell?What is congestion?
Whether congestion is related to placement or routing?What are clock trees?What are clock tree types?
Which layer is used for clock routing and why?What is cloning and buffering?What are placement blockages?
How slow and fast transition at inputs effect timing for gates?
What is antenna effect?
What is logic optimization and give some methods of logic optimization.What is the significance of negative slack?
What is signal integrity? How it affects Timing?
What is IR drop? How to avoid .how it affects timing?
What is EM and it effects?
What is a grid .why we need and different types of grids?
What is core and how u will decide w/h ratio for core?What is effective utilization and chip utilization?What is latency?
 Give the types?How the width of metal and number of straps calculated for power and ground?What is negative slack ?
 How it affects timing?What is track assignment?
In which layer do you prefer for clock routing and why?If in
your design has reset pin, then it’ll affect input pin or output pin or both?
 During power analysis, if you are facing IR drop problem, then how did u avoid?Define antenna problem and
 how did u resolve these problem?How delays vary with different PVT conditions? Show the graph.Explain the flow of physical design
 and inputs and outputs for each step in flow.What is cell delay and net delay?What are delay models and what is the difference
 between them?What is wire load model?What does SDC constraints has?
Differentiate between a Hierarchical Design and flat design?Which is more complicated when u have a 48 MHz and 500 MHz clock design?
Name few tools which you used for physical verification?What are the input files will you give for primetime correlation?
What are the algorithms used while routing? Will it optimize wire length?How will you decide the Pin location in block level 
design?If the routing congestion exists between two macros, then what will you do?How will you place the macros?How will you
 decide the die size?If lengthy metal layer is connected to diffusion and poly, then which one will affect by antennaproblem?
If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using7LM?
In your project what is die size, number of metal layers, technology, foundry, number of clocks?
How many macros in your design?What is each macro size and no. of standard cell count?
How did u handle the Clock in your design?
What are the Input needs for your design?
What is SDC constraint file contains?How did you do power planning?How to find total chip power?How to calculate core ring width, macro ring width and strap or trunk width?How to find number of power pad and IO power pads?What are the problems faced related to timing?
How did u resolve the setup and hold problem?
What is signal integrity? How it affects Timing?* 
 What are types of routing?
What is core and how u will decide w/h ratio for core?* What is effective utilization and chip utilization?
What is latency? Give the types?
What are the steps involved in designing an optimal pad ring?
What are the steps that you have done in the design flow?
What are the issues in floor plan?
How much aspect ratio should be kept (or have you kept) and what is the utilization?*
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
After adding stripes also if you have hot spot what to do?
Why higher metal layers are preferred for Vdd and Vss?
What are clock tree types?H tree, Balanced tree, X tree, Clustering tree, Fish bone
What is cloning and buffering?
Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating thecell.Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease thedealy.What parameters (or aspects) differentiate Chip Design & Block level design??


How do you place macros in a full chip design?
What are inputs for Star RC extraction.
inputs for PT (how it works and what format you take design)
how congestion you check what what was the ration, and how you fixed
What happen if you have insertion delay (apart for timing violation)
Floor planning, why we need .lib for floorplaning (apart from the power info)
Explain PD flow
how CLKBUF is differentiating with normal buffer, what if we use normal buffer.
latch up internal structure
why endcap, internal structure and how u differentiate with filler cell
What are all inputs u need for floorplan ?
What are the information present in LEF file?
What is END CAP cells ?
Why we check hold for fast fast corner ?
At which edge we will check setup and hold ?
if in case u havent provided lef then what will u do ?
What is useful skew?
what is DECAP cells ?
What are the steps for fixing setup and hold violations?
What is antenna violation how will u fix it ?
In antenna violation fixing why we are going for higher layers in metal jogging?
What maximum skew u used in your design ?
What is your insertion delay in that case ?
What is clk buffer and normal delay buffer?
What will you do if a path has  both setup and hold violations?
What is false path and multi cycle path?
what is LVT HVT SVT cells ?
How big was your previous design..?(Expectation was block size and gate count )
Hands on experience on PnR tools.
What were the challenges faced in your design and how did you overcome.?
How do you use the blockage technique effectively to reduce congestion.?
What are the types of blockages.?
Challenges in 28nm Technology.
How to fix Setup and Hold fixes..?
Buffer insertion technique, how the setup and hold varies with the buffer location(between source and destination)
What is antenna effect and the measures taken to over come.
Explain useful Skew technique
what type of challenges u faced in your design?
 what are the drastically changes come when u move from 180 nm to 28nm?
What is NDR? 
what are the timing challenges u faced in ur design. and how did u fixed?
what is Antenna effect. how do u fix. 
which tool u used for sign off.
how can you resolve EM issues in your design.
what is tap cell. why we use it.
Explain latchup effect
IF u face congestion in ur design during routing stage. how will u fix it. 
what are the inputs of red hawk.




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