Saturday, 8 August 2015


Routing Concept In Physical Design

After the floorplanning and placement steps in the design, routing needs to be done. Routing is nothing but connecting the various blocks in the chip with one another. Until now, the blocks were only just placed on the chip. Routing also is spilt into two steps

1. Global Routing:

It basically plans the overall connections between all the blocks and the nets. Its main aim is to minimize the total interconnect length, minimize the critical path delay. It determines the track assignments for each interconnect.

a. The chip is divided into small blocks. These small blocks are called routing bins. The size of the routing bin depends on the algorithm the tool uses. Each routing bin is also called a gcell. The size of this gcell depends on the tool.Each gcell has a finite number of horizontal and vertical tracks. Global routing assigns nets to specific gcells but it does not define the specific tracks for each of them. The global router connects two different gcells from the centre point of each gcell.

b. Track Assignment: The Global router keeps track of how many interconnections are going in each of direction. This is nothing but the routing demand. The number of routing layers that are available depend on the design and also, if the die size is more, the greater the routing tracks. Each routing layer has a minimum width spacing rule, and its own routing capacity. For Example: For a 5 metal layer design, if Metal 1, 4, 5 are partially up for inter-cell connections, pin, VDD, VSS connections, the only layers which are routable 100% are Metal2 and Metal3. So if the routing demand goes over the routing supply, it causes Congestion. Congestion leads to DRC errors and slow runtime

2. Detailed Routing:

In this step, the actual connection between all the nets takes place. It creates the actual via and metal connections. The main objective of detailed routing is to minimize the total area, wire length, delay in the critical paths. It specifies the specific tracks for the interconnection; each layer has its own routing grid, rules. During the final routing, the width, layer, and exact location of the interconnection are decided.After detailed routing is complete, the exact length and the position of each interconnect for every net in the design is known. The parasitic capacitance, resistance can now is extracted to determine the actual delays in the design. The parasitic extraction is done by extraction tools. This information is back annotated and the timing of the design is now calculated using the actual delays by the Static Timing Analysis Tool. After timing is met and all other verification is performed such as LVS, etc, the design is sent to the foundry to manufacture the chip.


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