Saturday, 8 August 2015

Clock Tree Synthesis

  Inputs for Clock Tree Synthesis
  • Placed Cell
  • CTS Constraints
  • Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }

      Goal of 
Clock Tree Synthesis

  • To  Balance Insertion Delay
  • To make Skew Zero. For this we this reason we will need to synthesize the clock tree
  • After CTS you should meet all the Hold Violations.


  • Is Skew is minimum and Insertion delay balanced.
  • Is Timing {Especially Hold} met, if not why?
  • If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.
  • Is std Cell Utilization acceptable at this stage
  • Check for Global Route Congestion
  • Check for Placement Legality.

Clock Tree Synthesis

The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is not propagated before CTS as shown in the picture. After CTS hold slack should improve. Clock tree begins at .sdc defined clock source and ends at stop pins of flop. There are two types of stop pins known as ignore pins and sync pins. ‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). ‘Ignore’ pins are ignored for timing analysis. If clock is divided then separate skew analysis is necessary.
  • Global skew achieves zero skew between two synchronous pins without considering logic relationship.
  • Local skew achieves zero skew between two synchronous pins while considering logic relationship.
  • If clock is skewed intentionally to improve setup slack then it is known as useful skew.
Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the rigidity tighter is the constraints.
In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer used for power routing is used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis. We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack. In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. Generally for 100k gates around 650 buffers are added

You may be also interested in below topics related to CTS


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  2. Outstanding information on PD for beginners >>>>>> :)

    Great .... appreciate your patience and knowledge ...

    if possible give more information using TCL scripts also

  3. which metal layers are used for clock routing ?and why?

    1. coming metal layers the top layers are for power,middle layers are allocated for clock routing, and last layers for signal purpose.
      for Ex: if we have 8 metal layers in a design,
      8,7 layers = power
      6,5 layers = clock
      4,3,2,1 layers = signal

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