Clock Tree Synthesis

  Inputs for Clock Tree Synthesis

   

• Placed Cell
• CTS Constraints
• Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }

      Goal of Clock Tree Synthesis

• To  Balance Insertion Delay
• To make Skew Zero. For this we this reason we will need to synthesize the clock tree
• After CTS you should meet all the Hold Violations.

Checks


• Is Skew is minimum and Insertion delay balanced.
• Is Timing {Especially Hold} met, if not why?
• If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.
• Is std Cell Utilization acceptable at this stage
• Check for Global Route Congestion
• Check for Placement Legality.

Clock Tree Synthesis

The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is not propagated before CTS as shown in the picture. After CTS hold slack should improve. Clock tree begins at .sdc defined clock source and ends at stop pins of flop. There are two types of stop pins known as ignore pins and sync pins. ‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). ‘Ignore’ pins are ignored for timing analysis. If clock is divided then separate skew analysis is necessary.

• Global skew achieves zero skew between two synchronous pins without considering logic relationship.
• Local skew achieves zero skew between two synchronous pins while considering logic relationship.
• If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the rigidity tighter is the constraints.

In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer used for power routing is used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis. We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack. In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. Generally for 100k gates around 650 buffers are added

You may be also interested in below topics related to CTS

• Terminology related to CTS
• How To fix Setup time Violation
• How To Fix Hold Time Violations
• Non Default Rules (NDR)
• HVT LVT SVT Cells
• Crosstalk
• Clock Buffer VS Normal Buffer

Scripts used in IC Compiler

Purpose and contents of the different scripts

1.init_design_icc.tcl 

The purpose of this file is to handoff a floorplanned CEL to the next step, which is the place_opt step.  Depending on the input format (MW, Verilog, DDC), it will read the appropriate files and also include the floorplan information provided via either a DEF input file, or already existing in the initial floorplanned CEL. 

If the input format is MW CEL, then no SDC constraints are loaded because they are assumed to be in the CEL already. The same is the case when loading DDC. It is only in the case of loading a verilog netlist, that the read_sdc  command is executed. 

We strongly recommend the usage of group paths to differentiate the Input-to-flop, Flop-to-Output and input-to-outputs feed through paths. That will improve the visibility during optimization. Just like with the SDC constraints, we will not create the group paths in case we enter with a MW cel or a DDC, but only in the case of entering with a pure ASIC flow, i.e. Verilog + sdc constraints. 

If certain floorplan constraints need to be added (such as placement or routing blockages), it is recommended to do this in this file, after the read-DEF section. 

This file is also setting up the different MV and MCMM portions. 

The output CEL created by this script is called: init_design_icc.

2. place_opt_icc.tcl 

The purpose of this script is to execute the placement and the placement based optimization. The default command that is executed is: 

place_opt -area_recovery -effort low 

That will provide the fastest result with still good QoR. After reading the initial CEL, created in the previous step, a file called icc_scripts/common_optimization_settings_icc.tcl  It is sourced. That file contains several settings that are recommended to be used during each of the optimization steps that follow. Because we also have the capability to execute a place_opt -cts, Which will also create the clock tree, it is required to also include the icc_scripts / common_cts_settings_icc.tcl file. That file specifies any clock tree related settings.

In addition to the default place_opt  command mentioned above, the script contains several other flavors of the 

place_opt  flow. These steps are put in comments and detailed explanation is provided for each of them. It is sufficient to comment out the undesired place_opt command, and uncomment the desired one. 

Eg if the user wants to run scan chain reordering in place_opt, he has to put comments before the default place_opt command, and uncomment the following lines: 

## What commands do you need when you want to optimize SCAN? 

# Read_def $ ICC_IN_SCAN_DEF_FILE 

# Redirect -file $ REPORTS_DIR / scan_chain_pre_ordering.rpt 

{Report_scan_chain} 

# Place_opt -area_recovery -optimize_dft -num_cpus $ ICC_NUM_CPUS 

The output CEL created in this step is called place_opt_icc. 

3. clock_opt_icc.tcl 

The purpose of this script is to execute the following three steps: 

•Clock tree synthesis and clock tree optimization (CTO) 

•Optimization of the post-cts design, including hold fixing based on virtual routes 

•Routing of the clock tree 

The file icc_scripts / common_cts_settings_icc.tcl  needs to be edited when you want to define any clock tree specific requirements. 

Examples are: 

•Clock tree exceptions.

•Non Default Routs (NDR's) to define e.g. double spacing for Xtalk avoidance on clock nets.

•Definition of clock tree master cells, for clock tree synthesis, or delay insertion during clock tree optimization (CTO).

•Inter clock delay balancing options specified via set_inter_clock_delay_options.

By default, ICC-RM does not execute any of these clock tree settings, because these are obviously very design dependent. 

In the clock_opt_icc.tcl script itself, there are 3 variants of the default clock_opt flow provided: 

•How to execute inter clock delay balancing?

•How to update the IO-latency after CTS?

•What commands to execute once your design becomes too congested after clock tree synthesis?

 The cell that is saved at the end is called  clock_opt_icc 

4. route_opt_icc.tcl 

The purpose of this script is to execute the routing step and proceed with the post route optimization in order to close the design for timing, DRC, and other design constraints. 

The command that is executed is the mainstream route_opt command, ie: 

•route_opt -effort low -xtalk_reduction 

 The tool will run by default in Xtalk Delta Delay (XDD) mode. 

 To enable static noise (aka glitches), as well as some advanced timing analysis capabilities (Arnoldi, timing windows, CRPR) you will have to edit the file:  

 ./icc_scripts/common_route_si_settings.tcl and uncomment the appropriate lines. 

The route_opt_icc.tcl scripts also contains (in comments), the required commands to run leakage power optimization, as well as some of the frequent used variants of route_opt: 

•Incremental route_opt optimization 

•Limiting the potential disturbance to the design using -size_only 

•Hold fixing only optimization 

  

The cell that is saved at the end is called route_opt_icc 

5.chip_finish_icc.tcl 

The purpose of this script is to provide the commands to execute the following chip finishing steps: 

• Antenna fixing against the plasma effect.

•Critical area reduction by executing timing driven detail route wire spreading ( Global route wire spreading is on by default as part of the Xtalk avoidance).

•Redundant via insertion.

•Standard cell filling.

•Timing driven Metal filling.

None of these steps are enabled by default, but can be controlled easily by editing the chipfinishing variables in the 

icc_setup.tcl file.

The cell that is saved at the end is called chip_finish_icc 

6. signoff_opt_icc.tcl 

This TCL script is opening the chipfinished cell, and executes run_signoff and signoff_opt. 

The run_signoff  command is running Synopsys's signoff extraction tools: Star-rcxt and  Primetime.  The ICC database in annotated with these signoff numbers. 

The signoff_opt  command is optimizing the design by making use of these signoff delays. After every optimization loop, the design will be incrementally extracted by Star-rcxt and incrementally timed by PTSI.  With this methodology, the output is a design that is signoff ready. 

This step is run by default after chipfinishing. If that step include metal filler, the signoff_opt_icc.tcl will also execute the required trim_eco_filler commands to clean up some of the modified filler polygons. 

7. outputs_icc.tcl  

The purpose of this script is to create several output files that will allow you to proceed with the next steps of the flow. 

Following files are generated: 

•Verilog netlist with and without PG connections 

•SBPF binary parasitic file (ASCII SPEF command is commented out) 

•GDSII streamout file

Questions Related to Clock Tree Synthesis

1. What is the goal of CTS? 
2. What are clock trees? 
3. What are clock tree types? 
4. How many clocks were there in this project? 
5. How will you use to take care  of all clocks used in your project?
6. Are they come from seperate external resources or PLL? 
7. How will you synthesize clock tree? 
8. Why double spacing and multiple vias are used related to clock? 
9. In which layer do you prefer for clock routing and why? 
10. What is latency? Give the types? 
11. Is it possible to have a zero skew in the design?
12. What are the difference between High Fanout synthesis and Clock tree synthesis?
13. Why CTS not done in synthesis?
14. why we prefer  clock buffer during cts, how they are different with normal buffer?
15. what is the target clock skew, clock latency target in your project?
16. Does the design have a PLL? How many clocks generated from PLL.
17. Are there derived clocks or complex clock generation circuitry? 
18. what do you mean by gated clocks, how many gated clocks were there in your project?
19. Is the clock gate used for timing or power? 
20. Available cells for clock tree?
21. Are there any special clock repeaters in the library? 
22. Are there any EM, slew or capacitance limits on these repeaters? 
23. Will the clock tree be shielded? If so, what are the shielding requirements? 
24. why buffers having balanced rise and fall delays are preferred in CTS 
25. Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
26. Explain the concept clock domains crossing, how will you synchronize clock in that case?
27. What is useful-skew mean? 
28. What is skew, how will you minimize it, if you dont minimize what all problem you can face because of it? 
29. Any special clock planning for block.
30. How do you account for clock tree insertion for scan?
31. Any clock generation block?
32. Have you used shielding rules for clock nets in your design?
33. How did you performed CTS for your block? How will you fix the clock latency violations?

Basics of IC Compiler

Basics of IC Compiler

The IC Compiler tool uses logic libraries to provide timing and functionality information for all
standard cells. In addition, logic libraries can provide timing information for hard macros, such
as RAMs. The tool supports logic libraries that use nonlinear delay models (NLDMs) and
Composite Current Source (CCS) models and automatically selects the timing models to use,
based on the contents of the logic libraries. If the logic libraries contain a mixture of both NLDM
and CCS models, by default, the tool uses the CCS capacitance and timing data; you can control
this by setting the lib_pin_using_cap_from_ccs and lib_cell_using_delay_from_ccs variables
before loading the libraries.

The link libraries are the logic libraries used to resolve cell references when the tool links the
design.The first library specified in the link_library variable is the main library.

The target libraries are the logic libraries that the tool uses to perform physical optimization.

The Milkyway reference libraries contain timing constraints and physical information about
the standard cells and macro cells in your logic library. In addition, these reference libraries
define the placement unit tile. The technology file provides technology-specific information,
such as the name and characteristics of each metal layer.

The physical library information is stored in the Milkyway design library. For each cell, the
Milkyway design library contains several views of the cell, which are used for different
physical design tasks. Commonly used views include

• The layout (CEL) view
• The place and route (FRAM) view
• The metal fill (FILL) view
• The power and ground connectivity (CONN) view

The error (ERR) view

If a Milkyway library does not already exist for your design, you need to create one and open it.

> Creating a Milkyway Design Library:

To create a Milkyway design library, use the create_mw_lib command;

Before working with the design, you must specify the Milkyway reference libraries used for the design. You can do this when you create the Milkyway design library with the create_mw_lib command or you
can do it later by using the set_mw_lib_reference command.

Note:

You can use the set_mw_lib_reference command to define the Milkyway reference libraries
associated with a Milkyway design library only when the Milkyway design library is closed. If the
design library is open, close it with the close_mw_lib command before defining the reference libraries.

> You can change the technology file and Milkyway reference libraries associated with your design
library.

Note: You can change the physical library information only when the Milkyway design library is closed.

> Before you process your design, you should use the check_library command to ensure that the logic libraries and physical libraries are correct and consistent.

By default, the check_library command performs consistency checking between the logic
libraries specified in the link_library variable and the physical libraries referenced in the current
Milkyway design library. If the check_library command reports any inconsistencies, you must fix
them before you process your design.

> The IC Compiler tool can read designs in Milkyway, .ddc, or ASCII (Verilog) format.

1) Reading a Design in Milkyway Format:

• The unit settings in the Milkyway design must be consistent with the unit settings in the main library (the first library in the link_library definition). To see the main library unit settings, use the report_lib command. To see the Milkyway design library unit settings, use the report_units command. The Milkyway design contains the floorplan information and timing constraints previously set on the design, so you do not need to annotate this information separately. 2) Reading a Design in .ddc Format:
• Readthe.ddcfileforthedesignbyusingtheimport_designscommand;Annotatethefloorplaninformationonthedesign.The .ddc design contains the scan chain information and timing constraints previously set on the design, so you do not need to annotate this information separately. If you are using a bottom-up flow, you must have FRAM views for all blocks in the top-level design.

> Note: Before reading the floorplan file, create the logical power and ground connections by using the derive_pg_connection command

> The tool maintains the SCANDEF data that describes scan chain characteristics and constraints, as well as the scan-stitched netlist. The netlist and SCANDEF data must be consistent with each other. To validate their consistency, use the check_scan_chain command.

> Validating the Floorplan Information ：

• Before running the place_opt command, run the check_physical_design command with the -stage pre_place_opt option.
  icc_shell> check_physical_design -stage pre_place_opt 
• Before running the clock_opt command, run the check_physical_design command
  with the -stage pre_clock_opt option.
  icc_shell> check_physical_design -stage pre_clock_opt 
• Before running the route_opt command, run the check_physical_design command with the -stage pre_route_opt option.
  icc_shell> check_physical_design -stage pre_route_opt 

> To validate the integrity of the design database, run the check_database command. By default, the check_database command verifies that

• The power and ground network is consistent
• There are no logical connections to physical-only cells
• The UPF data is consistent, if it exists
• The design has been uniquified and contains hierarchy preservation data
  To perform only the logical checks, use the -netlist option. To perform only the physical checks, use the -physical option. You can increase the verbosity of the generated messages by setting the -verbosity option to medium or high (the default is low).
  You should run the check_database command

• After reading a design in ASCII format using the read_def command
• Before running application commands, such as change_names, create_block_abstraction, place_opt, clock_opt, and route_opt. This can help save runtime in the case of a data error
• Before using the write_verilog command.

> use the derive_pg_connection command  to creates the logical power and ground connections for leaf cells, hierarchical cells, and physical-only cells in both single-voltage and multivoltage designs.

• To show the logical power and ground connections made by the derive_pg_connection command, use the report_cell_physical –connections command. You should rerun the derive_pg_connection command whenever the power and ground connections have changed, such as
  • After design planning
  • After using logic ECO to modify the design
  • After chip-finishing tasks

• If the design does not yet have power and ground ports, use the -create_ports top option to create these ports.

• If the design already has logical power and ground connections but you want to regenerate these connections, use the remove_pg_network -top command to remove the existing power and ground network before you run the derive_pg_connection command. By default, the derive_pg_connection command does not change existing power and ground pin connections. To reconnect the power and ground pins, use the -reconnect option when you run the derive_pg_connection command.

Note that the -reconnect option of the derive_pg_connection command does not reconnect tie-off nets.

》TLUPlus is a binary table format that stores the RC coefficients. The TLUPlus models enable accurate RC extraction results by including the effects of width, space, density, and temperature on the resistance coefficients.

• The map file, which matches the layer and via names in the Milkyway technology file with the names in the ITF file.

For multicorner-multimode designs, use the set_tlu_plus_files command to specify the TLUPlus files for each scenario. The set_tlu_plus_files command only applies to the current scenario.

After specifying the TLUPlus files, you should validate them by running the check_tlu_plus_files command.

> The operating conditions of a design include the process, voltage, and temperature parameters under which the chip is intended to operate. The tool analyzes and optimizes the design under the conditions you specify.

For multicorner-multimode designs, specify an operating condition for each scenario in the design.

Note: The link path should contain only the maximum library.

To find out which libraries are defined as the maximum and minimum libraries, use the list_libs command. In the generated report, the uppercase letter “M” appears next to the maximum library, and the lowercase letter “m” appears next to the minimum library.

> Advanced on-chip variation (AOCV) is an optional method of accuracy improvement that determines varying derating factors for different clock paths based on the path lengths.

Setting Timing Constraints

At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input delay or output delay for each I/O port. This requirement ensures that all signal paths are constrained for timing.

To model the clock tree effects for placement before running clock tree synthesis, you should also define the uncertainty, latency, and transition constraints for each clock by using the set_clock_uncertainty, set_clock_latency, and set_clock_transition commands.

The tool does not optimize paths that are not constrained for timing. Before proceeding, use the check_timing command to verify that all paths are constrained. If the check_timing command reports unconstrained paths, run the report_timing_requirements command to verify that the unconstrained paths are false paths (the check_timing command considers false paths unconstrained).

remove_ideal_network -all  This command removes ideal_network attributes, latencies, and transition times.

For multicorner-multimode designs, you must define timing constraints for each scenario.

Selecting the Delay Calculation Method

By default, the tool uses the Elmore delay model for preroute delay calculation and the Arnoldi delay model for routed clock and postroute delay calculation. To change the delay calculation model, use the set_delay_calculation_options command.

For preroute delay calculation, the tool computes delays based on estimated parasitic data for the nets. You can choose either Elmore or asymptotic waveform evaluation (AWE) as the delay model. The AWE delay model provides better accuracy and better correlation with postroute delay calculation.

For routed clock delay calculation and for postroute delay calculation, you can choose either Arnoldi or Elmore as the delay model. The Arnoldi delay model provides better accuracy and better correlation with PrimeTime delay calculation, especially for smaller geometries and for highly resistive nets.

You can use the compare_delay_calculation command to compare Elmore and Arnoldi results of sample delay calculations in your design. If the results are similar between the two methods, use the faster Elmore method. Otherwise, if you need the additional accuracy, use the Arnoldi method.

By default, the tool does not include crosstalk delta delays in the delay calculations. To extract coupling capacitances and include crosstalk delta delays in the postroute delay calculations, enter the following command:

icc_shell> set_si_options -delta_delay true 

Defining the Buffer Strategy for Optimization

During the optimization step, the place_opt command introduces buffers and inverters to fix timing and DRC violations. However, this buffering strategy is local to some critical paths. The buffers and inverters that are inserted might become excess later because critical paths change during the course of optimization. You can reduce the excess buffer and inverter counts after place_opt by using the set_buffer_opt_strategy command, as shown in the following example:

icc_shell> set_buffer_opt_strategy -effort low
This buffering strategy does not degrade the quality of results (QoR).

If you use the set_dont_use command to set the dont_use attribute on cells BUF1 and BUF2 , the tool uses cells BUF1 and BUF2 to fix hold violations, but not setup and DRC violations.

Enabling Tie Cell Insertion

A tie cell is a special-purpose standard cell whose output is constant high or constant low and is used to hold the input of another cell at the given constant value.

High-Fanout Net Synthesis

During placement and optimization, the IC Compiler tool does not buffer clock nets as defined by the create_clock command, but it does, by default, buffer other high-fanout nets, such as resets or scan enables, using a built-in high-fanout synthesis engine.

The high-fanout synthesis engine does not buffer nets that are set as ideal nets or nets that are disabled with respect to design rule constraints.

Inserting Port Protection Diodes

The IC Compiler tool can automatically insert protection diodes on subdesign ports to prevent antenna violations at the top level. You insert the port protection diodes after floorplanning but before starting placement.

Performing Placement and Optimization 

The place_opt command performs coarse placement, high-fanout net synthesis, physical optimization, and legalization. In addition, it can perform clock tree synthesis, scan chain reordering, and power optimization.

Performing Power Optimization 

Leakage dissipation is low when the threshold voltage is high and vice versa. Moreover, switching delay is increased when threshold voltage is high. So, using high-threshold-voltage cells to reduce the leakage can violate the timing constraints of the design. If the logic library supports cells with multiple threshold voltages, using cells with a lower threshold voltage for timing-critical paths and cells with a higher threshold voltage for other paths can reduce the leakage power without violating the delay.

During leakage-power optimization, the tool improves the leakage power only if it does not degrade timing.

Creating Multibit Register Banks

You can use the register banking flow to merge single-bit registers to form multibit register banks during placement and optimization.

Creating multibit register banks reduces

• The design area due to the smaller area of one multibit register bank compared to that of multiple single-bit registers
• The clock tree power consumption due to the smaller number of clock tree buffers

Analyzing the Placement Area Utilization

The default utilization is calculated as: (non-fixed_standard_cell_area + fixed_standard_cell_area) / (total_area – blocked_area)

whereas non-fixed-only utilization is calculated as: (non-fixed_standard_cell_area) / (total_area – fixed_standard_cell_area – blocked_area) 

Reporting Quality-of-Results

You can generate a report on the quality of results (QoR) for the design in its current state by using the create_qor_snapshot command (or by choosing Timing > Create QoR Snapshot in the GUI). This command measures and reports the quality of the design in terms of timing, design rules, area, power, congestion, clock tree synthesis, routing, and so on.

Performing Magnet Placement

To improve congestion for a complex floorplan or to improve timing for the design, you can use magnet placement to specify fixed objects as magnets and have the tool move their connected standard cells close to them.

For best results, perform magnet placement before standard cells are placed.

Magnet placement allows cells to be overlapped by default. To prevent overlapping of cells, you can set the magnet_placement_disable_overlap variable to true, changing it from its default of false.

Refining Placement

If your design shows large timing or violations after you run the place_opt command, adjust the place_opt options and rerun place_opt.

If your design shows small timing or violations after you run place_opt, run psynopt to fix these violations.

If your design has congestion violations after you run place_opt, rerun place_opt with high-effort congestion reduction (-congestion option). If your design still has congestion violations, you can refine the placement to fix these violations.

Physical Design Interview Question With Answers Part 2

Q.1 what are the other solution other than  increasing power line width and providing more number of straps to IR drop? 

Ans  below are some of the solution to IR drop problem

        Spreading the macros 

        Spreading standard cells 

        Usage of suitable blockage 

Q.2 Which is suitable place to insert buffer, in order to fix setup violation in reg to reg path? Is it near to launch or setup flop, Justify your answer?? 

Ans:- Buffer insertion is one of the method to overcome setup violation, Other methods are sizing of cells, Minimizing the data path etc. Lets assume that only  insertion of  buffer will solve the problem, then insert them Near to capture flop, Because there could be a chance other paths may be  passing  or originating from the launch flop. In that case  buffer insertion may could hamper others paths of launch flipflop. there is a chance it will improve all those paths or degrade. If all  paths have violation in launch flop also, then we can insert buffer near to launch flop. It could improve slack.

Q.3 How do you decide  best floorplan? 

Q.4 What are the challenges in the project?

Ans - Above answer you need to give according to your project common challenges could be  power planning- because of lots of IR drop  issue

      -could be  power target-because  more dynamic and leakage power 

      -It could be floorplanning issues in placing  macro.  

      - It could be CTS and CTO, because there may be chance you have to handle lots of clocks and clock domain crossing (CDC)

      -you might be facing challenges in timing fixtures

      -you might be facing library preparation, you may need to find some inconsistency in libraries. 

Q.5 )How will you synthesize clock tree? 

-Single clock-normal synthesis and optimization 

-Multiple clocks-Synthesis each clock separately 

-Multiple clocks with domain crossing-Synthesis each clock separately and balance the skew 

Q.6)How many clocks were there in this project

-It is specific to your project ,More number of the clocks more challenges you will face.

Q.7) How will you take care of all clocks? 

Ans -Multiple clocks --> synthesize separately --> skew Balancing-->optimization of clock tree 

Q.8) Are they come from separate external resources or Phase locked loop (PLL)? 

 -If it is from separate clock sources then balancing skew between these clock sources becomes challenging. 

-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy. 

Q.9)Why buffers are used in clock tree? 

 To balance skew (i.e. flop to flop delay) 

set_false_path Versus set_disable_timing in PrimeTime SI Crosstalk Analysis

set_false_path will prevent timing analysis from being performed on a path or paths. 

set_disable_timing will break the timing arc along a path or paths. With regards to 

crosstalk analysis, when an arc is broken with set_disable_timing edges will not 

physically propagate forward and will not cause downstream aggression. This could lead 

to optimistic crosstalk analysis. If there is a true edge that should be propagated for 

cross talk analysis and you only want to suppress the timing analysis of the path, then it is 

recommended to use set_false_path rather than set_disable_timing. If the edge cannot truly propagate past a point then set_disable_timing can be used to disable the path

Q.10)What is cross talk? 

Switching of the signal in one net can interfere neighboring net due to cross coupling 

capacitance.This affect is known as  Xtalk. Cross talk may lead setup or hold violation. 

Q.11) How can you avoid cross talk? 

-Double spacing, It means less capacitance, which ultimately results in less cross talk 

 -Multiple vias, which means less resistance and ultimately less RC delay 

 -Shielding,  which provide constant cross coupling capacitance

 -Buffer insertion can give strength the victim strength 

Q.12) How shielding avoids cross talk problem? What exactly happens there? 

-Crosstalk noise which is coupled to ground VSS (or power (VDD)) since shielding of  layers are 

connected to either power or ground

Frequently Asked Question in Physical Design Interviews

Click here for more questions

Questions                                                                                       Next Page

1. Tell me about your project experience?
2. What are technology node you worked on?
3. How Many Tape out you did? 
4. which customer/client you have worked with?

Questions Based on Floor Planning

1. What all checks you will perform before starting floor planning?
2. What are inputs given to the floor planning stage?
3. What kind of blockages you have given to your last project?
4. How you will determine the distance between two macros?
5. what is the size of your block?
6. what are general guidelines you followed for Macro placement?
7. How many macros and standard cell were there in your block?
8. how will you place macro?
9. In your design memories are there but not connected anywhere, where you will place the memory?
10. if your design is 8 layer and your block is 4 layer, how will you place.

Question Based on Placement and Route

1. How many blockages are there in your design, how will you solve blockages
2. whether routing is possible in HALO
3. How will you solve routing congestion
4. How many type of congestion were there in your design
5. How will you find the distance between two macros
6. how you use to do routing
7. How will you solve the congestion when utilization and cell density is more?

Question Based on STA & CTS

1. What is goal of CTS?
2. What are inputs to CTS?
3. What is the target skew?
4. what are inputs you have given in CTS
5. how will you solve setup violation
6. what is hold, how will you solve it
7. suppose your design is of 500 mhz frequency, setup and hold are fix. If frequency is increased to 750 mhz, what will happen to setup and hold
8. how will you build clock tree, describe the procedure
9. what is slew, what is relation between transition and slew
10. how you use to do cts
11. what is virtual clock
12. how will you save time in cts optimizations
13. what are false path
14. How signal integrity impact setup and hold violation?
15. How to fix setup and hold violation after p & r?

Question Based on Physical Verfication

1. what are the files getting evaluated during LVS stage

Miscellaneous Questions

 For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select and Why?
What is partial floor plan?  
 What are the steps that you have done in the design flow?What are the issues in floor plan?
How can you estimate area of block?
How much aspect ratio should be kept (or have you kept) a
what is the utilization?
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
 
After adding stripes also if you have hot spot what to do?
What is threshold voltage? How it affect timing?
What is content of lib, lef, sdc? 
What is meant by 9 track, 12 track standard cells?
What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
What is setup Time and hold time? Why there are ? What if setup Violates and hold violates?In a circuit, for reg to reg path ...
Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
How R and C values are affecting time?How ohm (R), fared (C) is related to second (T)?What is transition? 
What if transition time is more?
What is difference between normal buffer and clock buffer?
What is antenna effect?
 What is ESD?
What is cross talk? How can you avoid?
How double spacing will avoid cross talk?
What is difference between HFN synthesis and CTS?What is hold problem? How can you avoid it?
What are the steps that you have done in the design flow?What are the issues in floor plan?
How can you estimate area of block?How much aspect ratio should be kept (or have you kept) and 
what is the utilization?How to calculate core ring and stripe widths?What if hot spot found in some area of block? 
How you tackle this?After adding stripes also if you have hot spot what to do?What is threshold voltage? 
What are DFM issues? What is the difference between synthesis and simulation?What is metal density
 metal slotting rule?What is OPC, PSM?Why clock is not synthesized in DC?What are high-Vt and low-Vt cells?
What corner cells contains?What is the difference between core filler cells and metal fillers?
How to decide number of pads in chip level design?What is tie-high and tie-low cells and where it is used?
What is DEF?
What are the steps involved in designing an optimal pad ring?
What is grided and gridless routing?What is a macro and standard cell?What is congestion?
Whether congestion is related to placement or routing?What are clock trees?What are clock tree types?
Which layer is used for clock routing and why?What is cloning and buffering?What are placement blockages?
How slow and fast transition at inputs effect timing for gates?
What is antenna effect?
What is logic optimization and give some methods of logic optimization.What is the significance of negative slack?
What is signal integrity? How it affects Timing?
What is IR drop? How to avoid .how it affects timing?
What is EM and it effects?
What is a grid .why we need and different types of grids?
What is core and how u will decide w/h ratio for core?What is effective utilization and chip utilization?What is latency?
 Give the types?How the width of metal and number of straps calculated for power and ground?What is negative slack ?
 How it affects timing?What is track assignment?
In which layer do you prefer for clock routing and why?If in
your design has reset pin, then it’ll affect input pin or output pin or both?
 During power analysis, if you are facing IR drop problem, then how did u avoid?Define antenna problem and
 how did u resolve these problem?How delays vary with different PVT conditions? Show the graph.Explain the flow of physical design
 and inputs and outputs for each step in flow.What is cell delay and net delay?What are delay models and what is the difference
 between them?What is wire load model?What does SDC constraints has?
Differentiate between a Hierarchical Design and flat design?Which is more complicated when u have a 48 MHz and 500 MHz clock design?
Name few tools which you used for physical verification?What are the input files will you give for primetime correlation?
What are the algorithms used while routing? Will it optimize wire length?How will you decide the Pin location in block level 
design?If the routing congestion exists between two macros, then what will you do?How will you place the macros?How will you
 decide the die size?If lengthy metal layer is connected to diffusion and poly, then which one will affect by antennaproblem?
If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using7LM?
In your project what is die size, number of metal layers, technology, foundry, number of clocks?
How many macros in your design?What is each macro size and no. of standard cell count?
How did u handle the Clock in your design?
What are the Input needs for your design?
What is SDC constraint file contains?How did you do power planning?How to find total chip power?How to calculate core ring width, macro ring width and strap or trunk width?How to find number of power pad and IO power pads?What are the problems faced related to timing?
How did u resolve the setup and hold problem?
What is signal integrity? How it affects Timing?* 
 What are types of routing?
What is core and how u will decide w/h ratio for core?* What is effective utilization and chip utilization?
What is latency? Give the types?
What are the steps involved in designing an optimal pad ring?
What are the steps that you have done in the design flow?
What are the issues in floor plan?
How much aspect ratio should be kept (or have you kept) and what is the utilization?*
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
After adding stripes also if you have hot spot what to do?
Why higher metal layers are preferred for Vdd and Vss?
What are clock tree types?H tree, Balanced tree, X tree, Clustering tree, Fish bone
What is cloning and buffering?
Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating thecell.Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease thedealy.What parameters (or aspects) differentiate Chip Design & Block level design??


How do you place macros in a full chip design?
What are inputs for Star RC extraction.
inputs for PT (how it works and what format you take design)
how congestion you check what what was the ration, and how you fixed
What happen if you have insertion delay (apart for timing violation)
Floor planning, why we need .lib for floorplaning (apart from the power info)
Explain PD flow
how CLKBUF is differentiating with normal buffer, what if we use normal buffer.
latch up internal structure
why endcap, internal structure and how u differentiate with filler cell
What are all inputs u need for floorplan ?
What are the information present in LEF file?
What is END CAP cells ?
Why we check hold for fast fast corner ?
At which edge we will check setup and hold ?
if in case u havent provided lef then what will u do ?
What is useful skew?
what is DECAP cells ?
What are the steps for fixing setup and hold violations?
What is antenna violation how will u fix it ?
In antenna violation fixing why we are going for higher layers in metal jogging?
What maximum skew u used in your design ?
What is your insertion delay in that case ?
What is clk buffer and normal delay buffer?
What will you do if a path has  both setup and hold violations?
What is false path and multi cycle path?
what is LVT HVT SVT cells ?
How big was your previous design..?(Expectation was block size and gate count )
Hands on experience on PnR tools.
What were the challenges faced in your design and how did you overcome.?
How do you use the blockage technique effectively to reduce congestion.?
What are the types of blockages.?
Challenges in 28nm Technology.
How to fix Setup and Hold fixes..?
Buffer insertion technique, how the setup and hold varies with the buffer location(between source and destination)
What is antenna effect and the measures taken to over come.
Explain useful Skew technique
what type of challenges u faced in your design?
 what are the drastically changes come when u move from 180 nm to 28nm?
What is NDR? 
what are the timing challenges u faced in ur design. and how did u fixed?
what is Antenna effect. how do u fix. 
which tool u used for sign off.
how can you resolve EM issues in your design.
what is tap cell. why we use it.
Explain latchup effect
IF u face congestion in ur design during routing stage. how will u fix it. 
what are the inputs of red hawk.




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