Questions Related to Clock Tree Synthesis

1. What is the goal of CTS? 
2. What are clock trees? 
3. What are clock tree types? 
4. How many clocks were there in this project? 
5. How will you use to take care  of all clocks used in your project?
6. Are they come from seperate external resources or PLL? 
7. How will you synthesize clock tree? 
8. Why double spacing and multiple vias are used related to clock? 
9. In which layer do you prefer for clock routing and why? 
10. What is latency? Give the types? 
11. Is it possible to have a zero skew in the design?
12. What are the difference between High Fanout synthesis and Clock tree synthesis?
13. Why CTS not done in synthesis?
14. why we prefer  clock buffer during cts, how they are different with normal buffer?
15. what is the target clock skew, clock latency target in your project?
16. Does the design have a PLL? How many clocks generated from PLL.
17. Are there derived clocks or complex clock generation circuitry? 
18. what do you mean by gated clocks, how many gated clocks were there in your project?
19. Is the clock gate used for timing or power? 
20. Available cells for clock tree?
21. Are there any special clock repeaters in the library? 
22. Are there any EM, slew or capacitance limits on these repeaters? 
23. Will the clock tree be shielded? If so, what are the shielding requirements? 
24. why buffers having balanced rise and fall delays are preferred in CTS 
25. Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
26. Explain the concept clock domains crossing, how will you synchronize clock in that case?
27. What is useful-skew mean? 
28. What is skew, how will you minimize it, if you dont minimize what all problem you can face because of it? 
29. Any special clock planning for block.
30. How do you account for clock tree insertion for scan?
31. Any clock generation block?
32. Have you used shielding rules for clock nets in your design?
33. How did you performed CTS for your block? How will you fix the clock latency violations?