Saturday, 19 March 2016

Questions Related to Clock Tree Synthesis

  1. What is the goal of CTS? 
  2. What are clock trees? 
  3. What are clock tree types? 
  4. How many clocks were there in this project? 
  5. How will you use to take care  of all clocks used in your project?
  6. Are they come from seperate external resources or PLL? 
  7. How will you synthesize clock tree? 
  8. Why double spacing and multiple vias are used related to clock? 
  9. In which layer do you prefer for clock routing and why? 
  10. What is latency? Give the types? 
  11. Is it possible to have a zero skew in the design?
  12. What are the difference between High Fanout synthesis and Clock tree synthesis?
  13. Why CTS not done in synthesis?
  14. why we prefer  clock buffer during cts, how they are different with normal buffer?
  15. what is the target clock skew, clock latency target in your project?
  16. Does the design have a PLL? How many clocks generated from PLL.
  17. Are there derived clocks or complex clock generation circuitry? 
  18. what do you mean by gated clocks, how many gated clocks were there in your project?
  19. Is the clock gate used for timing or power? 
  20. Available cells for clock tree?
  21. Are there any special clock repeaters in the library? 
  22. Are there any EM, slew or capacitance limits on these repeaters? 
  23. Will the clock tree be shielded? If so, what are the shielding requirements? 
  24. why buffers having balanced rise and fall delays are preferred in CTS 
  25. Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
  26. Explain the concept clock domains crossing, how will you synchronize clock in that case?
  27. What is useful-skew mean? 
  28. What is skew, how will you minimize it, if you dont minimize what all problem you can face because of it? 
  29. Any special clock planning for block.
  30. How do you account for clock tree insertion for scan?
  31. Any clock generation block?
  32. Have you used shielding rules for clock nets in your design?
  33. How did you performed CTS for your block? How will you fix the clock latency violations?


  1. This comment has been removed by the author.

  2. Positive site, where did u come up with the information on this posting?I have read a few of the articles on your website now, and I really like your style. Thanks a million and please keep up the effective work. fake college diploma


  4. IEEE Project Domain management in software engineering is distinct from traditional project deveopment in that software projects have a unique lifecycle process that requires multiple rounds of testing, updating, and faculty feedback. A IEEE Domain project Final Year Projects for CSE system development life cycle is essentially a phased project model that defines the organizational constraints of a large-scale systems project. The methods used in a IEEE DOmain Project systems development life cycle strategy Project Centers in India provide clearly defined phases of work to plan, design, test, deploy, and maintain information systems.

    This is enough for me. I want to write software that anyone can use, and virtually everyone who has an internet connected device with a screen can use apps written in JavaScript. JavaScript Training in Chennai JavaScript was used for little more than mouse hover animations and little calculations to make static websites feel more interactive. Let’s assume 90% of all websites using JavaScript use it in a trivial way. That still leaves 150 million substantial JavaScript Training in Chennai JavaScript applications.

  5. As Logistics & Transportation is on-demand, we at Cellebre Technologies being a Logistics and Transportation, app development company offers Logistics Solutions.
    Transportation App Development Company