- What is slack?
- What is SDC constraint file contains?
- Delay of a cell depends on which factors ?
- Write Setup and Hold equations?
- Where do you get the WLM's? Do you create WLM's? How do you specify?
- In which case inserting a buffer will solve the setup timing?
- What is cross talk? How it affects timing.
- How can you avoid cross talk?
- How does shielding avoids Xtalk problem?
- Explain how more space helps in reducing Xtalk ?
- How buffer can be used in victim to avoid crosstalk?
- What are the problems faced related to timing?
- How did you resolve the setup and hold problem?
- How delays vary with different PVT conditions? Show the graph.
- What is cell delay and net delay?
- What are delay models and what is the difference between them?
- What is cloning and buffering?
- What is the derate value that can be used?
- What are corner and mode you checked timing during sign-off? have you kept same dearte values for all corners and mode or you have changed?
- What all the factors on which derating value depends?
- What factors decides the setup time of flip-flop?
- What is metastability?
- Do slowing down the frequency help in fixing hold time violation?
- slowing down the clock frequency helps in fixing setup time violations?
- Timing analysis and correlation b/w PnR and signoff?
- Explain the concept of false path?
- What are multi-cycle paths? Give example.
- How operating voltage can be used to satisfy timing?
- please suggest some method to overcome setup time and Hold time violations?
- What is the difference between local-skew, global-skew and useful-skew?
- What are factor does delay depends? How net delay and gate delay contribute to delay
- What are delay models and difference between them?
- What does SDC constraints has?
- What is wire load model?
- Hold time does not depend on clock. Is it true? If so why?
- What are the various timing-paths which should be taken care in STA?
- What are setup and hold time violations? How can they be eliminated?
- What is virtual clock why it is required to define it?
- What are the limitations in increasing the power supply to reduce delay?
- How to resolve max-trans & max-cap?
- What is fixed first max-trans, max-cap OR setup,hold?
- What is OCV , why do we need?
- What is the difference b/w OCV and PVT.
- Why do we have timing exceptions?
- What is path based and graph based analysis?
- What should we do if we want to include analog macro in the extraction?
- Type of techniques around periphery of block to maintain timing.
- Techniques to minimize number of hold buffers.
- What point in design, we look at hold timing?
- Were design blocks multimode?
- Single set or multiple set of constraints (for clock)
- Any experience in timing closure/ECO?
- What format did you get your ECO file? In Tcl script format or Graphical based format?
- Who set up primetime tool for design (like setting constraints)?
- For STA, do you need to create constraints for different operating modes like system mode or test mode?
- Techniques for I/O interface timing closure.
- Experience with Multimode/Single mode and multi corner blocks?
- Did top level person provide Tcl scripts?
- PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
- DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
- Have you done crosstalk analysis in your design?
- If you have undriven flops during check timing report, how will you proceed?
- If you have timing violations from a memory where the logic count is proper and
- constraints are also validated, how do you solve this?
- How do you fix Noise violation?
- How does upsizing of driver of victim help to fix noise violation?
Saturday 19 March 2016
STA Interview Questions Part 4
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