Saturday 19 March 2016

STA Interview Questions Part 4

  1. What is slack? 
  2. What is SDC constraint file contains? 
  3. Delay of a cell depends on which factors ? 
  4. Write Setup and Hold equations? 
  5. Where do you get the WLM's? Do you create WLM's? How do you specify? 
  6. In which case inserting a buffer will solve the setup timing? 
  7. What is cross talk? How it affects timing.
  8. How can you avoid cross talk? 
  9. How does shielding avoids Xtalk problem?
  10. Explain how more space helps in reducing Xtalk ?
  11. How buffer can be used in victim to avoid crosstalk? 
  12. What are the problems faced related to timing? 
  13. How did you resolve the setup and hold problem? 
  14. How delays vary with different PVT conditions? Show the graph. 
  15. What is cell delay and net delay? 
  16. What are delay models and what is the difference between them? 
  17. What is cloning and buffering? 
  18. What is the derate value that can be used? 
  19. What are  corner and mode  you checked  timing during sign-off? have you kept same dearte values for all corners and mode or you have changed? 
  20. What all the factors on which derating value depends? 
  21. What factors decides the setup time of flip-flop? 
  22. What is metastability? 
  23. Do slowing down the frequency help in fixing hold time violation? 
  24. slowing down the clock frequency helps in fixing setup time violations? 
  25. Timing analysis and correlation b/w PnR and signoff?
  26. Explain the concept of false path?
  27. What are multi-cycle paths? Give example. 
  28. How operating voltage can be used to satisfy timing? 
  29. please suggest some method to overcome setup time and Hold time violations?
  30. What is the difference between local-skew, global-skew and useful-skew? 
  31. What are factor does delay depends? How net delay and gate delay contribute to delay
  32. What are delay models and difference between them?
  33. What does SDC constraints has?
  34. What is wire load model? 
  35. Hold time does not depend on clock. Is it true? If so why? 
  36. What are the various timing-paths which should be taken care in STA?  
  37. What are setup and hold time violations? How can they be eliminated? 
  38. What is  virtual clock why it is required to define it? 
  39. What are the limitations in increasing the power supply to reduce delay? 
  40. How to resolve max-trans & max-cap?
  41. What is fixed first max-trans, max-cap OR setup,hold?
  42. What is OCV , why do we need?
  43. What is the difference b/w OCV and PVT.
  44. Why do we have timing exceptions?
  45. What is path based and graph based analysis?
  46. What should we do if we want to include analog macro in the extraction?
  47. Type of techniques around periphery of block to maintain timing.
  48. Techniques to minimize number of hold buffers.
  49. What point in design, we look at hold timing?
  50. Were design blocks multimode?
  51. Single set or multiple set of constraints (for clock)
  52. Any experience in timing closure/ECO?
  53. What format did you get your ECO file?  In Tcl script format or Graphical based format?
  54. Who set up primetime tool for design (like setting constraints)?
  55. For STA, do you need to create constraints for different operating modes like system mode or test mode?
  56. Techniques for I/O interface timing closure.
  57. Experience with Multimode/Single mode and multi corner blocks?
  58. Did top level person provide Tcl scripts?
  59. PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
  60. DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
  61. Have you done crosstalk analysis in your design?
  62. If you have undriven flops during check timing report, how will you proceed?
  63. If you have timing violations from a memory where the logic count is proper and 
  64. constraints are also validated, how do you solve this?
  65. How do you fix Noise violation? 
  66. How does upsizing of driver of victim help to fix noise violation?

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