Sunday, 28 February 2016

Physical Design (VLSI) Interview Questions Links

  • Physical Design interview Questions

  1. Physical Design interview Questions With Answers P...
  2. Physical Design Interview Question With Answers Part 2
  3. Physical Design Interview Question Part 1
  4. Physical Design Interview Question Part 2
  5. Physical Design Interview Question Part 3
  6. Physical Design (Floorplanning) interview Question...
  7. Physical Design (Power planning) Interview Questio...
  8. Frequently Asked Question in Physical Design Inter...
  9. Frequently Asked Question Part 2
  10. Questions Related to Power Planning, IR drop and Low power
  11. Questions Related to Clock Tree Synthesis
  12. Physical Design Interview Question Part 6


        STA Interview Question

Physical Design (Power planning) Interview Question Part 5


  1. . How will you do power planning? 
  2.  Power estimation
  3.  power pads estimation (core & IO) 
  4. core ring width calculation
  5. EMIR considerations
  6. SSO considerations
  7. What are preroutes in your design? 
  8. How to power route multiVDD design?
  9.  Power domains, partitioning, power routing for multi domains, placement of power switches?
  10.  What are the various views of a macro or a cell?
  11.  What is the macro placement guidelines?
  12. What all checks will you perform after Floor planning?
  13. What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
  14. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
  15. How did you define your power structure for full chip? 
  16. How will you start power planning for your design?
  17. EMIR & low power:
  18. How power is related with clock frequency? 
  19. Can we achieve lower power with more than one voltage supply?
  20. Different low power techniques?
  21. methods of leakage reduction? 
  22. What are the vectors of dynamic power? 
  23. How can you reduce dynamic power? 
  24. If you have both IR drop and congestion how will you fix it? 
  25. Is increasing power line width and providing more number of straps are the only solution to IR drop? 
  26. Why higher metal layers are preferred for Vdd and Vss? 
  27. What is IR drop? How it affects timing? 
  28. What is EM and it effects? how to resolve EM?
  29. Techniques to avoid IR problems? Dynamic & Static
  30. Do we have inactive blocks that we can shut off to reduce leakage power?
  31. What are Retention registers?
  32. Do we have blocks that can run at slower rate in certain modes? Can we reduce the 
  33. voltage during those modes?
  34. Give the various techniques you know to minimize power consumption for CMOS logic? 
  35. Give the expression for CMOS switching power dissipation? 
  36. List out the factors affecting power consumption on a chip? 
  37. Any custom routes of analog/power? What were the requirements of custom routes?
  38. Any experience in low power techniques?
  39. Any experience with multi Vt libraries?
  40. What is total Static & dynamic power consumption in your design?

Physical Design (Floorplanning) interview Question Part 4

1. Die size estimation:

2. How will you decide best floorplan? 

3. how to decide Aspect ratio? 

4.how to decide Macro placement ?

5. What is the target die size?

6.What is the expected utilization?

7. Does the area estimate include power/signal routing? 

8.What gates/mm2 has been assumed?

9.how to decide no. of routing layers?

10. Any special power routing requirements?

12. Please draw the overall floorplan ?

13. Is there an existing floorplan available in DEF? 

14. What are the number and type of macros (memory, PLL, etc.)?

15. Are there any analog blocks in the design? 

16. Placement of PLL? Analog placement requirements

17. Did you receive block size, pin locations from top level person?

18. How will you do floorplanning?(with out having data flow details)

19. How would you go about floorplanning when you have lots(hundreds) of macros?

20. What are the general guidelines to be followed when doing floorplanning?

21. how to decide Full chip IO ring: 

22. how to decide Total number of pins/pads and Location? 

23. how to decide Is the design pad limited? 

24. Number of digital I/O pins/pads?

25. Number of analog signal pins/pads? 

26. Number of power/ground pins/pads?

27. Will this chip use a wire bond/flipchip package? 

28. How IOSSO taken care? 

29. What ESD protection used for the IO ring? 

30. If flipchip, is it I/O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide?

Physical Design Interview Question Part 3

1. How many blocks/chips designed in your total years of Experience?

2. What is the latest project you finished? Was it block level implementation or full-chip implementation?

3. What is the design application?

4. Input is RTL or gate level netlist?

5. Explain Netlist(or RTL)-gdsii flow?

6. What are the input needs for your design? 

7. In which field are you interested? 

8. What is the most challenging task you handled? 

9. What are the challenges you faced in P&R flow? 

10. What parameters (or aspects) differentiate Chip Design and Block level design? 

12. Differentiate between a Hierarchical Design and flat design? 

13. What is the difference between soft macro and hard macro?

14. What are Ips?

15. What are the challenges you will see in lower technology?

16. What scan techniques being used?

17. Experience with timing closure & congestion issues?

18. Any experience with ECO (functional or timing ECO).

19. Towards the end of the project, what are some of the issues that can pop up , and 

20. how can they be fixed?

21. If you have shifted from one tool to another one, how long did it take to ramp up 

on the new tool?

22. What is the difference between a latch and a flip-flop?

23. On what basis we decide the clock frequency in any design?

24. Define threshold voltage? 

25. How does the size PMOS & NMOS transistors increases the threshold voltage? 

26.What is the effect of temperature on threshold voltage? 

27.What is the effect of gate voltage on mobility? 

28. What is the effect of temperature on mobility? 

29. If  we invert o/p of D flip-flop in the ip how does it will behave?

30.Design a circuit to divide input frequency by 2?

31. What is the maximum drive strength of standard buffers and inverters are available in your design? 

32. Why we increase the size and strength of inverters in buffer design? What will happen if you user inverter or buffer of maximum strength and size? 

33. What does lef and lib file contains?

34. What is generally in the x axis and y axis and what is linear line in any library(NLDM)?

35. What are the high speed and low speed cells?


36. What is the exact meaning of a capacitance?

Saturday, 20 February 2016

STA Interview Question Part 3


  1. What should we do if we want to include analog macro in the extraction?
  2. Type of techniques around periphery of block to maintain timing.
  3. Techniques to minimize number of hold buffers.
  4. What point in design, we look at hold timing?
  5. Were design blocks multimode?
  6. Single set or multiple set of constraints (for clock)
  7. Any experience in timing closure/ECO?
  8. What format did you get your ECO file?  In Tcl script format or Graphical based format?
  9. Who set up primetime tool for design (like setting constraints)?
  10. For STA, do you need to create constraints for different operating modes like system mode or test mode?
  11. Techniques for I/O interface timing closure.
  12. Experience with Multimode/Single mode and multi corner blocks?
  13. Did top level person provide Tcl scripts?
  14. PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
  15. DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
  16. Have you done crosstalk analysis in your design?
  17. If you have undriven flops during check timing report, how will you proceed?
  18. If you have timing violations from a memory where the logic count is proper and constraints are also validated, how do you solve this?
  19. How do you fix Noise violation? 
  20. How does upsizing of driver of victim help to fix noise violation?

STA Interview Questions Part 2

  1. Timing analysis and correlation b/w PnR and signoff?
  2. What do you mean by false path? Explain with an example? 
  3. Explain the concept of multi-cycle paths with PT command? 
  4. How operating voltage can be used to satisfy timing? 
  5. How to solve setup time and Hold time violations in the design?
  6. What is the difference between local-skew & global-skew? 
  7. What do you mean by useful skew, what is the advantage of it?
  8. What is cell delay and net delay? 
  9. What are delay models and difference between them?
  10. What does SDC constraints has?
  11. What is wire load model? 
  12. Hold time does not depend on clock. Is it true? If so why? 
  13. What do you mean by timing-paths? what are the timing path need to be taken care in STA?  
  14. What do you mean by setup violation and hold time violations? How can they be eliminated? 
  15. What is meant by virtual clock definition and why do i need it? 
  16. how does  increasing the power supply to reduce delay? 
  17. How to resolve max-trans & max-cap?
  18. What is fixed first max-trans, max-cap OR setup,hold?
  19. What is OCV , why do we need?
  20. What is the difference b/w OCV and PVT.
  21. Why do we have timing exceptions?
  22. What is path based and graph based analysis?


STA Interview Questions Part 1

What is slack?

What is SDC constraint file contains?

Delay of a cell depends on which factors ?

Write Setup and Hold equations?

Where do you get the WLM's? Do you create WLM's? How do you specify?

In which case inserting a buffer will solve the setup timing?

What is cross talk? How it affects timing.

How can you avoid cross talk?

what is  shielding ? how doe it prevents  cross talk ?

How spacing helps in reducing crosstalk noise?

How buffer can be used in victim to avoid crosstalk?

What are the problems faced related to timing?

How did you resolve the setup and hold problem?

How does delays varies with different PVT conditions? please explain with the help of graph.

What is cell delay and net delay?

What are different delay models  available and what are the difference between them?

What is cloning and buffering?

What is the derate value that can be used?

What are the corners you check for timing sign-off? Is there any changes in the derate value for each corner?

Where do you mean by the de-rating value? What are the factors that decide the de-rating values?

factor?

What factors decides the setup time of flip-flop?

What is metastability?

In a system with insufficient hold time, will slowing down the clock frequency help?

Physical Design Interview Question Part 2


  1. How many blocks/chips designed in your total years of Experience?
  2. What is the latest project you finished? Was it block/full-chip?
  3. What is the design application?
  4. Input is RTL or gate level netlist?
  5. Explain Netlist(or RTL)-gdsii flow?
  6. What are the input needs for your design? 
  7. In which field are you interested? 
  8. What is the most challenging task you handled? 
  9. What is the most challenging job in P&R flow?
  10. What parameters (or aspects) differentiate Chip Design and Block level design? 
  11. List down difference between a flat and hierarchical design? 
  12. What is the difference between soft macro and hard macro?
  13. What are the challenges seen as technology shrinks?
  14. What scan techniques being used?
  15. Experience with timing closure & congestion issues?
  16. Any experience with ECO (functional or timing ECO).
  17. what are issues you face during tapeout time?
  18. If you have shifted from one tool to another one, how long did it take to ramp up 
  19. on the new tool?
  20. What is the difference between a latch and a flip-flop?
  21. what all the parameters on which clock frequency depends in design?
  22. Define threshold voltage? 
  23. How do you size NMOS and PMOS transistors to increase the threshold voltage? 
  24. how threshold voltage is dependent on temperature? 
  25. What is the effect of gate voltage on mobility? 
  26. What is the effect of temperature on mobility? 
  27. Design a circuit to divide input frequency by 2?

Physical Design Interview Question Part 1


  1. Explain concept of   cross talk? 
  2. How can you overcome cross talk problem? 
  3. what is shielding? how it avoid avoids crosstalk problem? 
  4. how spacing h reducing crosstalk noise? 
  5. Why double spacing and multiple vias are used related to clock? 
  6. where do you insert buffer to avoid crosstalk? how buffer insertion solve the problem?
  7. Difference between Chip Design and Block level design? 
  8. What are the ways to place macros in a full chip design? 
  9. what are the differences between Hierarchical Design and flat design? 
  10. Why 500 MHz clock design is complex than 48Mhz design? 
  11. What all tools used in physical verification? 
  12. what are the inputs you will give in physical verification
  13. how will you solve the congestion between two macros? 
  14. what all parameters you will consider while estimating die size? 
  15. What is each macro size and number of standard cell count? 
  16. Depends on your design. 
  17. What are the input needs for your design?  
  18. What does SDC (Synopsys design contraint)  file contains? 
  19. how will give Clock definitions ?
  20. what are timing Timing exception, how will you constraint them?
  21. what is Input and Output delays, what are prime time  commands for it?
  22. How did you do power planning? 
  23. Explain, how will you find number of power pad and IO power pads? 
  24. How the  number of power straps calculate? 
  25. How to find total power of chip, What are the problems you can  faced with respect to timing? 
  26. what is  setup and hold problem, how will you solve it?
  27. which is preferable layer for clock routing and why? 
  28. what do you mean by IR drop problem, how will you overcome by this problem? 
  29. what is  antenna effect, how does it impact the and how would you resolve antennae effect problem? 
  30. How are the PVT conditions? Describe using graph?
  31. Describe the physical design flow?
  32. what all the  and inputs and outputs for each step of physical design? 
  33. What is cell delay and net delay, how will you reduce this delays? 
  34. What are  the different timing delay models available? 
  35. What is wire load model (WLM)?  
  36. Why higher metal layers are preferred for power? 
  37. What do you mean by logic optimization techniques, how it will work?
  38. what is slack, how will you calculate slack?
  39. what are the parameters on which slack depends on?
  40. What do you mean by of negative slack, how will u make it positive?  
  41. What is EM and it effects? 
  42. What are types of routing ?  
  43. What do you mean by clock latency? what are the  types of clock latecies? 
  44. What is track assignment in routing stage? 


Sunday, 14 February 2016

Physical Design interview Questions With Answers Part 1

Q.1) In what all area of physical design you have worked on?

Ans) Answer to this question depends expertise and to the requirement for

which you have been interviewed.


Q.2) what all low power techniques, you have used? How low power and latest

technologies are related?


Q.3) what input vector control  leakage reduction method?

Ans) Leakage current of a gate is also input dependent. Hence, we need to find the set of inputs

which gives least leakage. By applying this minimum leakage vector decreases the leakage current of the circuit  in  standby mode.


This method also called input vector controlled method of leakage reduction.


Q.4)How can you reduce dynamic power?

Ans) -Reduce switching activity by designing good RTL

 -Clock gating

 -Architectural improvements

 -Reduce supply voltage

 -Use multiple voltage domains-Multi vdd


Q.5)What are the vectors of dynamic power?

Ans) Voltage and Current

Q.6)How will you Computes a target IR drop value in the core from the target IR drop value?

Ans) Target IR drop in the core = <target IR drop from the package-to-I/O-to-core> –<IR drop

from package to core boundary>

(IR drop from package to core boundary = <IR drop in package> + <IR drop in bonding

wires> + <IR drop at I/O cells>)・IR drop is calculated by the unit of Power Domain for

multi power voltages.