Saturday, 20 February 2016

STA Interview Questions Part 2

  1. Timing analysis and correlation b/w PnR and signoff?
  2. What do you mean by false path? Explain with an example? 
  3. Explain the concept of multi-cycle paths with PT command? 
  4. How operating voltage can be used to satisfy timing? 
  5. How to solve setup time and Hold time violations in the design?
  6. What is the difference between local-skew & global-skew? 
  7. What do you mean by useful skew, what is the advantage of it?
  8. What is cell delay and net delay? 
  9. What are delay models and difference between them?
  10. What does SDC constraints has?
  11. What is wire load model? 
  12. Hold time does not depend on clock. Is it true? If so why? 
  13. What do you mean by timing-paths? what are the timing path need to be taken care in STA?  
  14. What do you mean by setup violation and hold time violations? How can they be eliminated? 
  15. What is meant by virtual clock definition and why do i need it? 
  16. how does  increasing the power supply to reduce delay? 
  17. How to resolve max-trans & max-cap?
  18. What is fixed first max-trans, max-cap OR setup,hold?
  19. What is OCV , why do we need?
  20. What is the difference b/w OCV and PVT.
  21. Why do we have timing exceptions?
  22. What is path based and graph based analysis?


1 comment:

  1. Tks very much for your post.

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