- Timing analysis and correlation b/w PnR and signoff?
- What do you mean by false path? Explain with an example?
- Explain the concept of multi-cycle paths with PT command?
- How operating voltage can be used to satisfy timing?
- How to solve setup time and Hold time violations in the design?
- What is the difference between local-skew & global-skew?
- What do you mean by useful skew, what is the advantage of it?
- What is cell delay and net delay?
- What are delay models and difference between them?
- What does SDC constraints has?
- What is wire load model?
- Hold time does not depend on clock. Is it true? If so why?
- What do you mean by timing-paths? what are the timing path need to be taken care in STA?
- What do you mean by setup violation and hold time violations? How can they be eliminated?
- What is meant by virtual clock definition and why do i need it?
- how does increasing the power supply to reduce delay?
- How to resolve max-trans & max-cap?
- What is fixed first max-trans, max-cap OR setup,hold?
- What is OCV , why do we need?
- What is the difference b/w OCV and PVT.
- Why do we have timing exceptions?
- What is path based and graph based analysis?
Saturday, 20 February 2016
STA Interview Questions Part 2
Posted by Akshay at 23:09