- . How will you do power planning?
- Power estimation
- power pads estimation (core & IO)
- core ring width calculation
- EMIR considerations
- SSO considerations
- What are preroutes in your design?
- How to power route multiVDD design?
- Power domains, partitioning, power routing for multi domains, placement of power switches?
- What are the various views of a macro or a cell?
- What is the macro placement guidelines?
- What all checks will you perform after Floor planning?
- What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
- If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
- How did you define your power structure for full chip?
- How will you start power planning for your design?
- EMIR & low power:
- How power is related with clock frequency?
- Can we achieve lower power with more than one voltage supply?
- Different low power techniques?
- methods of leakage reduction?
- What are the vectors of dynamic power?
- How can you reduce dynamic power?
- If you have both IR drop and congestion how will you fix it?
- Is increasing power line width and providing more number of straps are the only solution to IR drop?
- Why higher metal layers are preferred for Vdd and Vss?
- What is IR drop? How it affects timing?
- What is EM and it effects? how to resolve EM?
- Techniques to avoid IR problems? Dynamic & Static
- Do we have inactive blocks that we can shut off to reduce leakage power?
- What are Retention registers?
- Do we have blocks that can run at slower rate in certain modes? Can we reduce the
- voltage during those modes?
- Give the various techniques you know to minimize power consumption for CMOS logic?
- Give the expression for CMOS switching power dissipation?
- List out the factors affecting power consumption on a chip?
- Any custom routes of analog/power? What were the requirements of custom routes?
- Any experience in low power techniques?
- Any experience with multi Vt libraries?
- What is total Static & dynamic power consumption in your design?
Sunday 28 February 2016
Physical Design (Power planning) Interview Question Part 5
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