Sunday 28 February 2016

Physical Design (Power planning) Interview Question Part 5

  1. . How will you do power planning? 
  2.  Power estimation
  3.  power pads estimation (core & IO) 
  4. core ring width calculation
  5. EMIR considerations
  6. SSO considerations
  7. What are preroutes in your design? 
  8. How to power route multiVDD design?
  9.  Power domains, partitioning, power routing for multi domains, placement of power switches?
  10.  What are the various views of a macro or a cell?
  11.  What is the macro placement guidelines?
  12. What all checks will you perform after Floor planning?
  13. What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
  14. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
  15. How did you define your power structure for full chip? 
  16. How will you start power planning for your design?
  17. EMIR & low power:
  18. How power is related with clock frequency? 
  19. Can we achieve lower power with more than one voltage supply?
  20. Different low power techniques?
  21. methods of leakage reduction? 
  22. What are the vectors of dynamic power? 
  23. How can you reduce dynamic power? 
  24. If you have both IR drop and congestion how will you fix it? 
  25. Is increasing power line width and providing more number of straps are the only solution to IR drop? 
  26. Why higher metal layers are preferred for Vdd and Vss? 
  27. What is IR drop? How it affects timing? 
  28. What is EM and it effects? how to resolve EM?
  29. Techniques to avoid IR problems? Dynamic & Static
  30. Do we have inactive blocks that we can shut off to reduce leakage power?
  31. What are Retention registers?
  32. Do we have blocks that can run at slower rate in certain modes? Can we reduce the 
  33. voltage during those modes?
  34. Give the various techniques you know to minimize power consumption for CMOS logic? 
  35. Give the expression for CMOS switching power dissipation? 
  36. List out the factors affecting power consumption on a chip? 
  37. Any custom routes of analog/power? What were the requirements of custom routes?
  38. Any experience in low power techniques?
  39. Any experience with multi Vt libraries?
  40. What is total Static & dynamic power consumption in your design?

No comments:

Post a Comment