Saturday, 19 March 2016

STA Interview Questions Part 4

  1. What is slack? 
  2. What is SDC constraint file contains? 
  3. Delay of a cell depends on which factors ? 
  4. Write Setup and Hold equations? 
  5. Where do you get the WLM's? Do you create WLM's? How do you specify? 
  6. In which case inserting a buffer will solve the setup timing? 
  7. What is cross talk? How it affects timing.
  8. How can you avoid cross talk? 
  9. How does shielding avoids Xtalk problem?
  10. Explain how more space helps in reducing Xtalk ?
  11. How buffer can be used in victim to avoid crosstalk? 
  12. What are the problems faced related to timing? 
  13. How did you resolve the setup and hold problem? 
  14. How delays vary with different PVT conditions? Show the graph. 
  15. What is cell delay and net delay? 
  16. What are delay models and what is the difference between them? 
  17. What is cloning and buffering? 
  18. What is the derate value that can be used? 
  19. What are  corner and mode  you checked  timing during sign-off? have you kept same dearte values for all corners and mode or you have changed? 
  20. What all the factors on which derating value depends? 
  21. What factors decides the setup time of flip-flop? 
  22. What is metastability? 
  23. Do slowing down the frequency help in fixing hold time violation? 
  24. slowing down the clock frequency helps in fixing setup time violations? 
  25. Timing analysis and correlation b/w PnR and signoff?
  26. Explain the concept of false path?
  27. What are multi-cycle paths? Give example. 
  28. How operating voltage can be used to satisfy timing? 
  29. please suggest some method to overcome setup time and Hold time violations?
  30. What is the difference between local-skew, global-skew and useful-skew? 
  31. What are factor does delay depends? How net delay and gate delay contribute to delay
  32. What are delay models and difference between them?
  33. What does SDC constraints has?
  34. What is wire load model? 
  35. Hold time does not depend on clock. Is it true? If so why? 
  36. What are the various timing-paths which should be taken care in STA?  
  37. What are setup and hold time violations? How can they be eliminated? 
  38. What is  virtual clock why it is required to define it? 
  39. What are the limitations in increasing the power supply to reduce delay? 
  40. How to resolve max-trans & max-cap?
  41. What is fixed first max-trans, max-cap OR setup,hold?
  42. What is OCV , why do we need?
  43. What is the difference b/w OCV and PVT.
  44. Why do we have timing exceptions?
  45. What is path based and graph based analysis?
  46. What should we do if we want to include analog macro in the extraction?
  47. Type of techniques around periphery of block to maintain timing.
  48. Techniques to minimize number of hold buffers.
  49. What point in design, we look at hold timing?
  50. Were design blocks multimode?
  51. Single set or multiple set of constraints (for clock)
  52. Any experience in timing closure/ECO?
  53. What format did you get your ECO file?  In Tcl script format or Graphical based format?
  54. Who set up primetime tool for design (like setting constraints)?
  55. For STA, do you need to create constraints for different operating modes like system mode or test mode?
  56. Techniques for I/O interface timing closure.
  57. Experience with Multimode/Single mode and multi corner blocks?
  58. Did top level person provide Tcl scripts?
  59. PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
  60. DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
  61. Have you done crosstalk analysis in your design?
  62. If you have undriven flops during check timing report, how will you proceed?
  63. If you have timing violations from a memory where the logic count is proper and 
  64. constraints are also validated, how do you solve this?
  65. How do you fix Noise violation? 
  66. How does upsizing of driver of victim help to fix noise violation?

Questions Related to Clock Tree Synthesis

  1. What is the goal of CTS? 
  2. What are clock trees? 
  3. What are clock tree types? 
  4. How many clocks were there in this project? 
  5. How will you use to take care  of all clocks used in your project?
  6. Are they come from seperate external resources or PLL? 
  7. How will you synthesize clock tree? 
  8. Why double spacing and multiple vias are used related to clock? 
  9. In which layer do you prefer for clock routing and why? 
  10. What is latency? Give the types? 
  11. Is it possible to have a zero skew in the design?
  12. What are the difference between High Fanout synthesis and Clock tree synthesis?
  13. Why CTS not done in synthesis?
  14. why we prefer  clock buffer during cts, how they are different with normal buffer?
  15. what is the target clock skew, clock latency target in your project?
  16. Does the design have a PLL? How many clocks generated from PLL.
  17. Are there derived clocks or complex clock generation circuitry? 
  18. what do you mean by gated clocks, how many gated clocks were there in your project?
  19. Is the clock gate used for timing or power? 
  20. Available cells for clock tree?
  21. Are there any special clock repeaters in the library? 
  22. Are there any EM, slew or capacitance limits on these repeaters? 
  23. Will the clock tree be shielded? If so, what are the shielding requirements? 
  24. why buffers having balanced rise and fall delays are preferred in CTS 
  25. Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
  26. Explain the concept clock domains crossing, how will you synchronize clock in that case?
  27. What is useful-skew mean? 
  28. What is skew, how will you minimize it, if you dont minimize what all problem you can face because of it? 
  29. Any special clock planning for block.
  30. How do you account for clock tree insertion for scan?
  31. Any clock generation block?
  32. Have you used shielding rules for clock nets in your design?
  33. How did you performed CTS for your block? How will you fix the clock latency violations?

Questions Related to Power Planning, IR drop and Low power

  1.  what is powerplanning, How you use to do i. Power estimation ii. power pads estimation (core & IO) iii. core ring width calculation iv. EMIR v. SSO 
  2.  What are preroutes in your design? 
  3.  How to power route multiVDD design?
  4. Power domains, partitioning, power routing for multi domains, placement of power switches?
  5. What are the various views of a macro or a cell?
  6.  What is the macro placement guidelines?
  7.  What all checks will you perform after Floor planning?
  8.  What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
  9. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
  10. How did you define your power structure for full chip? 
  11. How will you start power planning for your design?                                                                                                                                                                                                                      EMIR & low power:
  12. How power is related with clock frequency? 
  13. Can we achieve lower power with more than one voltage supply?
  14. Different low power techniques?
  15. methods of leakage reduction? 
  16. What are the vectors of dynamic power? 
  17. How can you reduce dynamic power? 
  18. If you have both IR drop and congestion how will you fix it? 
  19. Is increasing power line width and providing more number of straps are the only 
  20. solution to IR drop? 
  21. Why higher metal layers are preferred for Vdd and Vss? 
  22. What is IR drop? How it affects timing? 
  23. What is EM and it effects? how to resolve EM?
  24. Techniques to avoid IR problems? Dynamic & Static
  25. Do we have inactive blocks that we can shut off to reduce leakage power?
  26. What are Retention registers?
  27. Give the various techniques you know to minimize power consumption for CMOS logic? 
  28. Give the expression for CMOS switching power dissipation? 
  29. List out the factors affecting power consumption on a chip? 
  30. Any custom routes of analog/power? What were the requirements of custom routes?
  31. Any experience in low power techniques?
  32. Any experience with multi Vt libraries?
  33. What is total Static & dynamic power consumption in your design?

Wednesday, 16 March 2016

Physical Design Interview Question With Answers Part 2

Q.1 what are the other solution other than  increasing power line width and providing more number of straps to IR drop? 

Ans  below are some of the solution to IR drop problem
        Spreading the macros 
        Spreading standard cells 
        Usage of suitable blockage 

Q.2 Which is suitable place to insert buffer, in order to fix setup violation in reg to reg path? Is it near to launch or setup flop, Justify your answer?? 
Ans:- Buffer insertion is one of the method to overcome setup violation, Other methods are sizing of cells, Minimizing the data path etc. Lets assume that only  insertion of  buffer will solve the problem, then insert them Near to capture flop, Because there could be a chance other paths may be  passing  or originating from the launch flop. In that case  buffer insertion may could hamper others paths of launch flipflop. there is a chance it will improve all those paths or degrade. If all  paths have violation in launch flop also, then we can insert buffer near to launch flop. It could improve slack.

Q.3 How do you decide  best floorplan? 

Q.4 What are the challenges in the project?
Ans - Above answer you need to give according to your project common challenges could be  power planning- because of lots of IR drop  issue

      -could be  power target-because  more dynamic and leakage power 
      -It could be floorplanning issues in placing  macro.  
      - It could be CTS and CTO, because there may be chance you have to handle lots of clocks and clock domain crossing (CDC)
      -you might be facing challenges in timing fixtures
      -you might be facing library preparation, you may need to find some inconsistency in libraries. 

Q.5 )How will you synthesize clock tree? 
-Single clock-normal synthesis and optimization 
-Multiple clocks-Synthesis each clock separately 
-Multiple clocks with domain crossing-Synthesis each clock separately and balance the skew 

Q.6)How many clocks were there in this project
-It is specific to your project ,More number of the clocks more challenges you will face.

Q.7) How will you take care of all clocks? 
Ans -Multiple clocks --> synthesize separately --> skew Balancing-->optimization of clock tree 

Q.8) Are they come from separate external resources or Phase locked loop (PLL)? 
 -If it is from separate clock sources then balancing skew between these clock sources becomes challenging. 
-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy. 

Q.9)Why buffers are used in clock tree? 
 To balance skew (i.e. flop to flop delay) 
set_false_path Versus set_disable_timing in PrimeTime SI Crosstalk Analysis
set_false_path will prevent timing analysis from being performed on a path or paths. 
set_disable_timing will break the timing arc along a path or paths. With regards to 
crosstalk analysis, when an arc is broken with set_disable_timing edges will not 
physically propagate forward and will not cause downstream aggression. This could lead 
to optimistic crosstalk analysis. If there is a true edge that should be propagated for 
cross talk analysis and you only want to suppress the timing analysis of the path, then it is 
recommended to use set_false_path rather than set_disable_timing. If the edge cannot truly propagate past a point then set_disable_timing can be used to disable the path

Q.10)What is cross talk? 
Switching of the signal in one net can interfere neighboring net due to cross coupling 
capacitance.This affect is known as  Xtalk. Cross talk may lead setup or hold violation. 

Q.11) How can you avoid cross talk? 
-Double spacing, It means less capacitance, which ultimately results in less cross talk 
 -Multiple vias, which means less resistance and ultimately less RC delay 
 -Shielding,  which provide constant cross coupling capacitance
 -Buffer insertion can give strength the victim strength 

Q.12) How shielding avoids cross talk problem? What exactly happens there? 
-Crosstalk noise which is coupled to ground VSS (or power (VDD)) since shielding of  layers are 

connected to either power or ground