Wednesday, 16 March 2016

Physical Design Interview Question With Answers Part 2

Q.1 what are the other solution other than  increasing power line width and providing more number of straps to IR drop? 

Ans  below are some of the solution to IR drop problem
        Spreading the macros 
        Spreading standard cells 
        Usage of suitable blockage 

Q.2 Which is suitable place to insert buffer, in order to fix setup violation in reg to reg path? Is it near to launch or setup flop, Justify your answer?? 
Ans:- Buffer insertion is one of the method to overcome setup violation, Other methods are sizing of cells, Minimizing the data path etc. Lets assume that only  insertion of  buffer will solve the problem, then insert them Near to capture flop, Because there could be a chance other paths may be  passing  or originating from the launch flop. In that case  buffer insertion may could hamper others paths of launch flipflop. there is a chance it will improve all those paths or degrade. If all  paths have violation in launch flop also, then we can insert buffer near to launch flop. It could improve slack.

Q.3 How do you decide  best floorplan? 

Q.4 What are the challenges in the project?
Ans - Above answer you need to give according to your project common challenges could be  power planning- because of lots of IR drop  issue

      -could be  power target-because  more dynamic and leakage power 
      -It could be floorplanning issues in placing  macro.  
      - It could be CTS and CTO, because there may be chance you have to handle lots of clocks and clock domain crossing (CDC)
      -you might be facing challenges in timing fixtures
      -you might be facing library preparation, you may need to find some inconsistency in libraries. 

Q.5 )How will you synthesize clock tree? 
-Single clock-normal synthesis and optimization 
-Multiple clocks-Synthesis each clock separately 
-Multiple clocks with domain crossing-Synthesis each clock separately and balance the skew 

Q.6)How many clocks were there in this project
-It is specific to your project ,More number of the clocks more challenges you will face.

Q.7) How will you take care of all clocks? 
Ans -Multiple clocks --> synthesize separately --> skew Balancing-->optimization of clock tree 

Q.8) Are they come from separate external resources or Phase locked loop (PLL)? 
 -If it is from separate clock sources then balancing skew between these clock sources becomes challenging. 
-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy. 

Q.9)Why buffers are used in clock tree? 
 To balance skew (i.e. flop to flop delay) 
set_false_path Versus set_disable_timing in PrimeTime SI Crosstalk Analysis
set_false_path will prevent timing analysis from being performed on a path or paths. 
set_disable_timing will break the timing arc along a path or paths. With regards to 
crosstalk analysis, when an arc is broken with set_disable_timing edges will not 
physically propagate forward and will not cause downstream aggression. This could lead 
to optimistic crosstalk analysis. If there is a true edge that should be propagated for 
cross talk analysis and you only want to suppress the timing analysis of the path, then it is 
recommended to use set_false_path rather than set_disable_timing. If the edge cannot truly propagate past a point then set_disable_timing can be used to disable the path

Q.10)What is cross talk? 
Switching of the signal in one net can interfere neighboring net due to cross coupling 
capacitance.This affect is known as  Xtalk. Cross talk may lead setup or hold violation. 

Q.11) How can you avoid cross talk? 
-Double spacing, It means less capacitance, which ultimately results in less cross talk 
 -Multiple vias, which means less resistance and ultimately less RC delay 
 -Shielding,  which provide constant cross coupling capacitance
 -Buffer insertion can give strength the victim strength 

Q.12) How shielding avoids cross talk problem? What exactly happens there? 
-Crosstalk noise which is coupled to ground VSS (or power (VDD)) since shielding of  layers are 

connected to either power or ground

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