VLSI Physical Design
Clock Tree Synthesis (CTS)
Static Timing Analysis (STA)
Low Power Design
Physical Design Course for Beginners
Careers in VLSI
Tuesday, 1 November 2016
Flip Flop Vs Latch
A flip-flop samples the inputs only at a clock event (rising edge, etc.)
A Latch samples the inputs continuously
whenever it is enabled
, that is, only when the enable signal is on. (or otherwise, it would be a wire, not a latch).
Flip-Flop are edge sensitive.
Latches are level sensitive.
Flipflop is sensitive to signal change and not on level. They can transfer data only at the single instant and data cannot be changed until next signal change.
Latch is sensitive to duration of pulse and can send or receive the data when the switch is on.
A flip-flop continuously checks its inputs and correspondingly changes its output only at times determined by clocking signal.
Latch is a device which continuously checks all its input and correspondingly changes its output, independent of the time determined by clocking signal.
It work’s on the basis of clock pulses.
It is based on enable function input
It is a edge trigerred , it mean that the output and the next state input changes when there is a change in clock pulse whether it may a +ve or -ve clock pulse.
It is a level trigerred , it mean that the output of present state and input of the next state depends on the level that is binary input 1 or 0.
VLSI Junction Team
Share to Twitter
Share to Facebook
Share to Pinterest