Tuesday 24 November 2015

Project Challenges

Below are few Challenges you may face during your project execution time 

  • -It may be power planning- because you found more IR drop
  • -It may be low power target-because you had more dynamic and leakage power
  • -It may be macro placement-because it had more connection with standard cells or macros
  • -It may be CTS-because you needed to handle multiple clocks and clock domain crossings
  • -It may be timing-because sizing cells in ECO flow is not meeting timing
  • -It may be library preparation-because you found some inconsistancy in libraries.
  • -It may be DRC-because you faced thousands of voilations
  • Monday 23 November 2015

    Frequently Asked Question Part 2

                                                                                                                               Previous Page

    * What is signal integrity? How it affects Timing?
    * What is IR drop? How to avoid IR drop .how it affects timing?
    * What is EM and it effects?
    * What is floor plan and power plan?
    * What are types of routing?
    * What is a grid .why we need and different types of grids?
    * What is core and how u will decide w/h ratio for core?
    * What is effective utilization and chip utilization?
    * What is latency? Give the types?
    * What is LEF?
    * What is DEF?
    * What are the steps involved in designing an optimal pad ring?
    * What are the steps that you have done in the design flow?
    * What are the issues in floor plan?
    * How can you estimate area of block?
    * How much aspect ratio should be kept (or have you kept) and what is the utilization?
    * How to calculate core ring and stripe widths?
    * What if hot spot found in some area of block? How you tackle this?
    * After adding stripes also if you have hot spot what to do?
    * What is threshold voltage? How it affect timing?
    * What is content of lib, lef, sdc?
    * What is meant my 9 track, 12 track standard cells?
    * What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
    * What is setup and hold? Why there are ? What if setup violation fix and hold violation fixtures?
    * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
    * How R and C values are affecting time?
    * How ohm (R), fared (C) is related to second (T)?
    * What is transition? What if transition time is more?
    * What is difference between normal buffer and clock buffer?
    * What is antenna effect? How it is avoided?
    * What is ESD?
    * What is cross talk? How can you avoid?
    * How double spacing will avoid cross talk?
    * What is difference between HFN synthesis and CTS?
    * What is hold problem? How can you avoid hold time violations?
    * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
    * What is partial floor plan?
    * What parameters (or aspects) differentiate Chip Design & Block level design??
    * How do you place macros in a full chip design?
    * Differentiate between a Hierarchical Design and flat design?
    * Which is more complicated when u have a 48 MHz and 500 MHz clock design?
    * Name few tools which you used for physical verification?
    * What are the input files will you give for primetime correlation?
    * What are the algorithms used while routing? Will it optimize wire length?
    * How will you decide the Pin location in block level design?
    * If the routing congestion exists between two macros, then what will you do?
    * How will you place the macros?
    * How will you decide the die size?
    * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
    * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
    * In your project what is die size, number of metal layers, technology, foundry, number of clocks?
    * How many macros in your design?
    * What is each macro size and no. of standard cell count?
    * How did u handle the Clock in your design?
    * What are the Input needs for your design?
    * What is SDC constraint file contains?
    * How did you do power planning?
    * How to find total chip power?
    * How to calculate core ring width, macro ring width and strap or trunk width?
    * How to find number of power pad and IO power pads?
    * What are the problems faced related to timing?
    * How did u resolve the setup and hold problem?
    * If in your design 10000 and more numbers of problems come, then what you will do?
    * In which layer do you prefer for clock routing and why?
    * If in your design has reset pin, then it’ll affect input pin or output pin or both?
    * During power analysis, if you are facing IR drop problem, then how did u avoid?
    * Define antenna problem and how did u resolve these problem?
    * How delays vary with different PVT conditions? Show the graph.
    * Explain the flow of physical design and inputs and outputs for each step in flow.
    * What is cell delay and net delay?
    * What are delay models and what is the difference between them?
    * What is wire load model?
    * What does SDC constraints has?
    * Why higher metal layers are preferred for Vdd and Vss?
    * What is logic optimization and give some methods of logic optimization.
    * What is the significance of negative slack?
    * How the width of metal and number of straps calculated for power and ground?
    * What is negative slack ? How it affects timing?
    * What is track assignment?
    * What is grided and gridless routing?
    * What is a macro and standard cell?
    * What is congestion?
    * Whether congestion is related to placement or routing?
    * What are clock trees?
    * What are clock tree types?
    * Which layer is used for clock routing and why?
    * What is cloning and buffering?
    * What are placement blockages?
    * How slow and fast transition at inputs effect timing for gates?
    * What is antenna effect?
    * What are DFM issues?
    * What is .lib, LEF, DEF, .tf?
    * What is the difference between synthesis and simulation?
    * What is metal density, metal slotting rule?
    * What is OPC, PSM?
    * Why clock is not synthesized in DC?
    * What are high-Vt and low-Vt cells?
    * What corner cells contains?
    * What is the difference between core filler cells and metal fillers?
    * How to decide number of pads in chip level design?
    * What is tie-high and tie-low cells and where it is used

    Sunday 22 November 2015

    High Fanout Synthesis

    As all of us knows fanout of the clock signal is high. Apart from that few of the signals are existed in design like reset ,clear and scan enable signals and etc..

    The signal nets which have more fanout compared to specified fanout is also known as HFN

    we all know that
    set_max_fanout <some number> during synthesis this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net.

    Why do we do this ?

    As we understanding HFN has lot of load obviously it has huge capacitance.

    And if we tried to report the timing it reports very huge cap violations and huge delays in the timing path.

    So to avoid this huge delays in timing path we are setting the same net as HFN.

    another way to set an HFN to synthesis tool: set_ideal_net <net name>

    This way the synthesis tool knows the specified net as a high fanout net and does not buffer them .

    Unified Power Format

    Files written to this standard annotate an electric design with the power and power control intent of that design. Elements of that annotation include:
    • Power Supplies: supply nets, supply sets, power states
    • Power Control: power switches
    • Additional Protection: level shifters and isolation
    • Memory retention during times of limited power: retention strategies and supply set power states
    • Refinable descriptions of the potential power applied to the electronic system: power states, transitions, a set of simstate, pg_type and function attributes of nets, and the -update argument to support the progressive refinement of the power intent.

    Saturday 21 November 2015

    Interface Logic Models

    Interface Logic Model (ILM) is a technique to model blocks in hierarchal VLSI implementation flow.
    It is a gate level model of a physical block where only the connections from the inputs to the first stage of flip-flops, and the connections from the last stage of flip-flops to the outputs are in the model, including the flip-flops and the clock tree driving these flip-flops. All other internal flip-flop to flip-flop paths are stripped out of the ILM.
    The advantage of ILM is that entire path ( clock to clock path) is visible at top level for interface nets unlike traditional block based hierarchal implementation flow. That gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.

    Wednesday 11 November 2015


    N-type metal-oxide-semiconductor logic uses n-type field effect transistors (MOSFETs) to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in an p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation.
    The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.


    P-type metal-oxide-semiconductor logic uses p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-type transistor body. This inversion layer, called the p-channel, can conduct holes between p-type "source" and "drain" terminals.
    The p-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, PMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation.
    The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate output and positive supply voltage, while a resistor is placed between the logic gate output and the negative supply voltage. The circuit is designed such that if the desired output is high, then the PUN will be active, creating a current path between the positive supply and the output.
    While PMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with PMOS FETs), it has several shortcomings as well. The worst problem is that there is a direct current (DC) through a PMOS logic gate when the PUN is active, that is, whenever the output is high, which leads to static power dissipation even when the circuit sits idle.
    Also, PMOS circuits are slow to transition from high to low. When transitioning from low to high, the transistors provide low resistance, and the capacitative charge at the output accumulates very quickly (similar to charging a capacitor through a very low resistance). But the resistance between the output and the negative supply rail is much greater, so the high-to-low transition takes longer (similar to discharge of a capacitor through a high resistance). Using a resistor of lower value will speed up the process but also increases static power dissipation.
    Additionally, the asymmetric input logic levels make PMOS circuits susceptible to noise

    CMOS Inverter

    CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.
    The image below shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage.
    On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.
    In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.
    The power supplies for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies. These do not apply directly to CMOS, since both supplies are really source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

    Start Point and End Point of STA

    Any given timing path need to begin from a valid startpoint and end on a valid endpoint.
    The following are valid startpoints:

    • A primary input port.
    • Capturing pin of a sequential cell (D pin of a flop, a latch or synchronous reset/set pins of a reset/set flop).
    The following are valid endpoints:
    • A primary output port.
    • Launching pin of a sequential cell (CK pin of a flop or EN pin of a latch).
    As evident from the number of start and end point types given above, any design with atleast two sequential cells, there can be 4 types of timing paths.
    • Input to Register - Starting on a primary input port and ending on a capturing pin of a register
    • Register to output - Starting on a launching pin of a flop and ending on an output port.
    • Register to Register - Starting on a launching pin of a flop and ending on a capturing pin of a register
    • Input to Output - Starting on a primary input port and ending on an output port.
    Any valid timing path should be one of the above types.
    There are several other types given by tools such as default, macro pins as startpoint and endpoint, which adds one additional startpoint type and one additional endpoint type and corresponding combinations of the timing paths. But, a macro in general can be considered as a register with many endpoints (input ports) and possibly many start points (clock pins).

    Tuesday 10 November 2015

    False Path

    A false path, as its name denotes is a timing path not required to meet its timing constraints for the design to function properly.

    In general all timing paths those are launched by a valid startpoint and captured by a valid endpoint impose setup and hold constraints. If the functionality of the design is such that the timing constraints need not be met on the path, it is a false path.

    Every false path needs to be informed to the STA tool. As the STA tool considers every path that originates at a valid startpoint and ends on a valid endpoint as a valid timing path that needs to be met.

    A situation where the design results in false paths is:
    There are two 2 input muxes in a design. Both of which are selected by a common select line.

    If you consider the signal B to be launched by a flop and Y to be captured by another flop, in no situation, there will be valid funtional path between B and Y.
    Reason: Assume the muxes select signal at top side when the select line is 0 and the bottom signal when select line is 1. When the select line is 0, B is selected by mux 1, but the mux 1 output (D) will not be selected by mux 2. But the static timing analysis tool will not consider this as an invalid path, it just looks for valid timing arcs, an there is a timing arc from B input to output of the first mux and then to the Y signal through the second mux.

    This is just a simple example of a false path. There can be many paths of this type in a large design. But, we cannot find each and every path and declare it as false. If this type of path is found in a clock muxing logic, then declaring a false path (I think set_disable_timing might be required for the paths in clock logic) through B and Y would be useful. If this type of path is found in a critical path of design, then it will be very useful to add a false path.

    When functional ports are multiplexed with test logic, the input and output delays added on these ports would also show up many false paths.

    If possible (timing is not critical and area is not critical), optimizing a false path is of no harm compared to declaring a functionally necessary path as a false path by mistake

    Static Power Dissipation

    Subthreshold conduction when the transistors are off

    Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current (called sub threshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

    Tunnelling current through gate oxide

    SiO2 is a very good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

    Leakage current through reverse-biased diodes

    Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

    Dynamic Power Dissipation

    Charging and discharging of load capacitance

    CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore in one complete charge/discharge cycle, a total of Q=CLVDD is thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device:  P = 0.5 C V^2 f .
    Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor \alpha, called the activity factor. Now, the dynamic power dissipation may be re-written as  P = \alpha C V^2 f .
    A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1. If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

    CTS Terminology

    • Stop (Sync) Pins: All clock pins of FF are called as Stop (Sync) Pins. The clock signal  should not propagate after reaching the syc/stop pin. This pin needs to considered for building the clock tree. 
    • Exclude (Ignore) pins: All non clock pins such as D pin of FF or combo logic’s inputs are called as Exclude (Ignore) pins. These pins are need not to be considered during the clock tree propagation.
    • Float (Implicit stop or macro model) pins: This is same as sync or stop pin but internal clock latency of that pin is taken into consideration while building the clock tree. Its a clock entry pin of hard macros and it needs to be considered while building the clock tree. But before considering this as sync pin, the macro’s internal tree needs to be balanced.
    • Explicit sync (stop) pins: Input of a combo logic is considered while building the clock tree. Mostly this comes to picture  whenever clock gating concept is used.
    • Explicit Exclude (Ignore) pins: Clock pin of a flip flop is not considered as sync/stop pin. This is also again due to the use of clock gating concept. Because while gating the clock, the clock signal will be given to an and gate.