Friday 31 May 2019

Product, EDA, Foundaries and service Companies that works in the field of VLSI

List of few Product companies, EDA companies and Foundaries who works in the field of VLSI, there are many companies but the popular ones captured here . There are many good service companies which works in VLSI domain,

Product Companies

  • AMD
  • Analog Devices
  • Apple
  • ARM
  • Broadcom
  • Cisco
  • Cypress Semiconductors
  • Google
  • Infineon Technologies AG
  • Intel
  • LG Soft
  • Microsemi
  • MosChip Semiconductor Technology Ltd
  • Nvidia
  • NXP
  • ON Semiconductor
  • Qualcomm
  • Samsung Electronics
  • STMicroelectronics
  • Texas Instrument
  • Western Digital

EDA Companies

  • Ansys
  • Cadence
  • Dorado
  • Mentor Graphics
  • Synosys
  • Xilinx


  • Global Foundaries
  • Intel
  • Samsung
  • TSMC
  • UMC

Top Service Companies

  • Atran
  • cientra
  • einfochip
  • Eximius
  • L & T
  • Mirafra
  • Open-Silicom
  • Open-Silicon
  • Sankalp semiconductor
  • Synapse Design
  • UST Global
  • whizchip
  • Wipro

Thursday 30 May 2019

What is Objective and challenges of Physical Design?

Since design and manufacturing of IC (Integrated circuits) could millions of dollars. Quality of chip also matters a lot to company. 

AIM of Physical design Engineer to acieve 
  •  Power
  •  Performance
  •  Area

This target is also known as PPA,

Saving of power (dynamic and static) lesser the heating of the circuit. If chip is going to be in battery operated system then power consumed by IC significantly results in battery drained off. less the power more time battery can run operate the device.

Performance term is associated with speed/frequency or we can say timing, faster the circuit performance will be greats.

Cost of manufacturing is directly proportional to area, if area of IC is more than more cost you need to pay to manufacturer. In order to save money in manufacturing preferable is more number of gate counts should be get manufacture in given amount of area.

Challenges in Physical design
  •  Achieve timing
  •  Congestion
  •  Manufacturing requirements such as DRC, DFM etc
  •  Meeting power numbers
  •  Delivery of the project timelines

As technology nodes is shrinking achieving above targets are becoming tougher and tougher. Identifying the issues at early stages is always good. In order to achieve target keep running sign off checks at regular interval of time. Re-spin of design is time consuming and non-productive way of working.

Every company aims to bring their product in market as soon as possible in order to beat the competition. So keeping in the mind objective and challenges a physical design engineer should work.

What is Physical Design?

The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components.

The main steps in the ASIC physical design flow are:

  • Design Netlist (after synthesis)
  • Floorplanning
  • Partitioning
  • Placement
  • Clock-tree Synthesis (CTS)
  • Routing
  • Physical Verification
  • GDS II Generation

Below are main sign off checks/Analysis in Physical Design

  • 1. Logical Equivalence Check
  • 2. Static Timing Analysis
  • 3. Power analysis (static and dynamic,  resistance checks etc)
  • 4. Low power Checks

Saturday 25 May 2019

Crosstalk in Physical Design

Crosstalk is the undesirable electrical interaction between two or more physically adjacent nets due to capacitive cross-coupling. As integrated circuit technologies advance toward smaller geometries, crosstalk effects become increasingly important compared to cell delays and net delays.

How to fix cross talk

1. using NDR (eg. double width and double spacing) rules on Nets
2. increase the drive strength of the driver cell of victim net
3. shielding can be one of the option 
4. Breaking the net by buffer insertion
5. Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur.