Wednesday 5 June 2019

How many macros and standard cell were there in your block?

Answer to this question is purely on the design specific, bu there are blocks without macros also, which is called purely standard cell cells blocks. As number of macros increased, analysis in the floor plan also increases, below are some checks which you have to do while handling large number of macro
1. Legalization of macros
2. connectivity of macros to standard cells, other macro and ports, ignoring of this point may cause the congestion and timing violation
3. while arranging the macros in floorplan consider macro to macro communication also
4. always keep some channel between the macro, in later stages this will help in hold buffering,

what is SDF files?

Standard Delay Format (SDF) is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between dynamic timing verification and static timing analysis.
It was originally developed as an OVI standard, and later modified into the IEEE format. Technically only the SDF version 4.0 onwards are IEEE formats.
It is an ASCII format that is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.
It has usually two sections: one for interconnect delays and the other for cell delays.
SDF format can be used for back-annotation as well as forward-annotation.

The Standard Delay Format (SDF) file stores the timing data generated by
EDA tools for use at any stage in the design process. The data in the SDF
file is represented in a tool-independent way and can include
  •  Delays: module path, device, interconnect, and port
  •  Timing checks: setup, hold, recovery, removal, skew, width, period, and nochange
  •  Timing constraints: path, skew, period, sum, and diff
  •  Timing environment: intended operating timing environment
  •  Incremental and absolute delays
  •  Conditional and unconditional module path delays and timing checks
  •  Design/instance-specific or type/library-specific data
  •  Scaling, environmental, and technology parameters

Throughout a design process, you can use several different SDF files. Some of these files can contain pre-layout timing data. Others can contain path constraint or post-layout timing data. The name of each SDF file is determined by the EDA tool. There are no conventions for naming SDF files.