Saturday, 8 August 2015


Why is timing analysis important when designing a chip?

STA Introduction

Timing is important because just designing the chip is not enough; we need to know how fast the chip is going to run, how fast the chip is going to interact with the other chips, how fast the input reaches the output etc…Timing Analysis is a method of verifying the timing performance of a design by checking for all possible timing violations in all possible paths.

  • Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations.
  • Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation
  • STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design.

Majorly Tool used

Prime Time (From Synopsys)

Input Required for STA

1. Netlist
2. .lib for standard cells
3. .lib for hard macros
4. SPEF/SDF files
5. Constraints files (.sdc)

Advanced Timing Analysis

Analysis Modes
 Data to Data Checks 
 Case Analysis 
 Multiple Clocks per Register 
 Minimum Pulse Width Checks 
 Derived Clocks 
 Clock Gating Checks 
 Netlist Editing 
 Clock Reconvergence Pessimism 
 Worst-Arrival Slew Propagation
 Debugging Delay Calculation 

PrimeTime Timing Models Support

PrimeTime offers the following timing models to address STA needs for IP, large hierarchical designs, and custom design:

  1. Quick Timing Model (QTM)  
  2. Extracted Timing Model (ETM)
  3.  Interface Logic Model (ILM)  
  4. Stamp Model


  1. short and clear explation to analog engineer like me

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