Thursday, 6 August 2015

Frequently Asked Question in Physical Design Interviews

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Questions                                                                                       Next Page
  1. Tell me about your project experience?
  2. What are technology node you worked on?
  3. How Many Tape out you did? 
  4. which customer/client you have worked with?

Questions Based on Floor Planning

  1. What all checks you will perform before starting floor planning?
  2. What are inputs given to the floor planning stage?
  3. What kind of blockages you have given to your last project?
  4. How you will determine the distance between two macros?
  5. what is the size of your block?
  6. what are general guidelines you followed for Macro placement?
  7. How many macros and standard cell were there in your block?
  8. how will you place macro?
  9. In your design memories are there but not connected anywhere, where you will place the memory?
  10. if your design is 8 layer and your block is 4 layer, how will you place.

Question Based on Placement and Route
  1. How many blockages are there in your design, how will you solve blockages
  2. whether routing is possible in HALO
  3. How will you solve routing congestion
  4. How many type of congestion were there in your design
  5. How will you find the distance between two macros
  6. how you use to do routing
  7. How will you solve the congestion when utilization and cell density is more?

Question Based on STA & CTS

  1. What is goal of CTS?
  2. What are inputs to CTS?
  3. What is the target skew?
  4. what are inputs you have given in CTS
  5. how will you solve setup violation
  6. what is hold, how will you solve it
  7. suppose your design is of 500 mhz frequency, setup and hold are fix. If frequency is increased to 750 mhz, what will happen to setup and hold
  8. how will you build clock tree, describe the procedure
  9. what is slew, what is relation between transition and slew
  10. how you use to do cts
  11. what is virtual clock
  12. how will you save time in cts optimizations
  13. what are false path
  14. How signal integrity impact setup and hold violation?
  15. How to fix setup and hold violation after p & r?

Question Based on Physical Verfication

1. what are the files getting evaluated during LVS stage

Miscellaneous Questions

  1. For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select and Why?
  2. What is partial floor plan?
  3. What are the steps that you have done in the design flow?What are the issues in floor plan?
  4. How can you estimate area of block?
  5. How much aspect ratio should be kept (or have you kept) a
  6. what is the utilization?
  7. How to calculate core ring and stripe widths?
  8. What if hot spot found in some area of block? How you tackle this?
  10. After adding stripes also if you have hot spot what to do?
  11. What is threshold voltage? How it affect timing?
  12. What is content of lib, lef, sdc?
  13. What is meant by 9 track, 12 track standard cells?
  14. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
  15. What is setup Time and hold time? Why there are ? What if setup Violates and hold violates?In a circuit, for reg to reg path ...
  16. Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
  17. How R and C values are affecting time?How ohm (R), fared (C) is related to second (T)?What is transition?
  18. What if transition time is more?
  19. What is difference between normal buffer and clock buffer?
  20. What is antenna effect?
  21. What is ESD?
  22. What is cross talk? How can you avoid?
  23. How double spacing will avoid cross talk?
  24. What is difference between HFN synthesis and CTS?What is hold problem? How can you avoid it?
  25. What are the steps that you have done in the design flow?What are the issues in floor plan?
  26. How can you estimate area of block?How much aspect ratio should be kept (or have you kept) and
  27. what is the utilization?How to calculate core ring and stripe widths?What if hot spot found in some area of block?
  28. How you tackle this?After adding stripes also if you have hot spot what to do?What is threshold voltage?
  29. What are DFM issues? What is the difference between synthesis and simulation?What is metal density
  30. metal slotting rule?What is OPC, PSM?Why clock is not synthesized in DC?What are high-Vt and low-Vt cells?
  31. What corner cells contains?What is the difference between core filler cells and metal fillers?
  32. How to decide number of pads in chip level design?What is tie-high and tie-low cells and where it is used?
  33. What is DEF?
  34. What are the steps involved in designing an optimal pad ring?
  35. What is grided and gridless routing?What is a macro and standard cell?What is congestion?
  36. Whether congestion is related to placement or routing?What are clock trees?What are clock tree types?
  37. Which layer is used for clock routing and why?What is cloning and buffering?What are placement blockages?
  38. How slow and fast transition at inputs effect timing for gates?
  39. What is antenna effect?
  40. What is logic optimization and give some methods of logic optimization.What is the significance of negative slack?
  41. What is signal integrity? How it affects Timing?
  42. What is IR drop? How to avoid .how it affects timing?
  43. What is EM and it effects?
  44. What is a grid .why we need and different types of grids?
  45. What is core and how u will decide w/h ratio for core?What is effective utilization and chip utilization?What is latency?
  46. Give the types?How the width of metal and number of straps calculated for power and ground?What is negative slack ?
  47. How it affects timing?What is track assignment?
  48. In which layer do you prefer for clock routing and why?If in
  49. your design has reset pin, then it’ll affect input pin or output pin or both?
  50. During power analysis, if you are facing IR drop problem, then how did u avoid?Define antenna problem and
  51. how did u resolve these problem?How delays vary with different PVT conditions? Show the graph.Explain the flow of physical design
  52. and inputs and outputs for each step in flow.What is cell delay and net delay?What are delay models and what is the difference
  53. between them?What is wire load model?What does SDC constraints has?
  54. Differentiate between a Hierarchical Design and flat design?Which is more complicated when u have a 48 MHz and 500 MHz clock design?
  55. Name few tools which you used for physical verification?What are the input files will you give for primetime correlation?
  56. What are the algorithms used while routing? Will it optimize wire length?How will you decide the Pin location in block level
  57. design?If the routing congestion exists between two macros, then what will you do?How will you place the macros?How will you
  58. decide the die size?If lengthy metal layer is connected to diffusion and poly, then which one will affect by antennaproblem?
  59. If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using7LM?
  60. In your project what is die size, number of metal layers, technology, foundry, number of clocks?
  61. How many macros in your design?What is each macro size and no. of standard cell count?
  62. How did u handle the Clock in your design?
  63. What are the Input needs for your design?
  64. What is SDC constraint file contains?How did you do power planning?How to find total chip power?How to calculate core ring width, macro ring width and strap or trunk width?How to find number of power pad and IO power pads?What are the problems faced related to timing?
  65. How did u resolve the setup and hold problem?
  66. What is signal integrity? How it affects Timing?* 
  67. What are types of routing?
  68. What is core and how u will decide w/h ratio for core?* What is effective utilization and chip utilization?
  69. What is latency? Give the types?
  70. What are the steps involved in designing an optimal pad ring?
  71. What are the steps that you have done in the design flow?
  72. What are the issues in floor plan?
  73. How much aspect ratio should be kept (or have you kept) and what is the utilization?*
  74. How to calculate core ring and stripe widths?
  75. What if hot spot found in some area of block? How you tackle this?
  76. After adding stripes also if you have hot spot what to do?
  77. Why higher metal layers are preferred for Vdd and Vss?
  78. What are clock tree types?H tree, Balanced tree, X tree, Clustering tree, Fish bone
  79. What is cloning and buffering?
  80. Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating thecell.Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease thedealy.What parameters (or aspects) differentiate Chip Design & Block level design??
  81. How do you place macros in a full chip design?
  82. What are inputs for Star RC extraction.
  83. inputs for PT (how it works and what format you take design)
  84. how congestion you check what what was the ration, and how you fixed
  85. What happen if you have insertion delay (apart for timing violation)
  86. Floor planning, why we need .lib for floorplaning (apart from the power info)
  87. Explain PD flow
  88. how CLKBUF is differentiating with normal buffer, what if we use normal buffer.
  89. latch up internal structure
  90. why endcap, internal structure and how u differentiate with filler cell
  91. What are all inputs u need for floorplan ?
  92. What are the information present in LEF file?
  93. What is END CAP cells ?
  94. Why we check hold for fast fast corner ?
  95. At which edge we will check setup and hold ?
  96. if in case u havent provided lef then what will u do ?
  97. What is useful skew?
  98. what is DECAP cells ?
  99. What are the steps for fixing setup and hold violations?
  100. What is antenna violation how will u fix it ?
  101. In antenna violation fixing why we are going for higher layers in metal jogging?
  102. What maximum skew u used in your design ?
  103. What is your insertion delay in that case ?
  104. What is clk buffer and normal delay buffer?
  105. What will you do if a path has  both setup and hold violations?
  106. What is false path and multi cycle path?
  107. what is LVT HVT SVT cells ?
  108. How big was your previous design..?(Expectation was block size and gate count )
  109. Hands on experience on PnR tools.
  110. What were the challenges faced in your design and how did you overcome.?
  111. How do you use the blockage technique effectively to reduce congestion.?
  112. What are the types of blockages.?
  113. Challenges in 28nm Technology.
  114. How to fix Setup and Hold fixes..?
  115. Buffer insertion technique, how the setup and hold varies with the buffer location(between source and destination)
  116. What is antenna effect and the measures taken to over come.
  117. Explain useful Skew technique
  118. what type of challenges u faced in your design?
  119.  what are the drastically changes come when u move from 180 nm to 28nm?
  120. What is NDR
  121. what are the timing challenges u faced in ur design. and how did u fixed?
  122. what is Antenna effect. how do u fix. 
  123. which tool u used for sign off.
  124. how can you resolve EM issues in your design.
  125. what is tap cell. why we use it.
  126. Explain latchup effect
  127. IF u face congestion in ur design during routing stage. how will u fix it. 
  128. what are the inputs of red hawk.
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  1. please add more questions about STA

  2. Hi Ariful, I have added few more question in miscellaneous section it includes the question from all the area