Generation of Integrated Circuits

As number of transistor, which can be fabricated in a single chip increased through generation, We believe more transistor and more complex IC's are yet to come.

SSI  (Small Scale Integration) introduced in 1964, Having transistors 1 - 10 and logic gates 1 - 12

MSI (Medium Scale Integration) introduced in 1968, Having transistors 10 - 500 and logic gates  13 - 99

LSI (Large Scale Integration) introduced in 1971, having transistors 500 - 20000 and logic gates 100 - 9999

VLSI (Very Large Scale Integeration) introduced in 1980, having transistors 20000-1000000 and logic gates 10000 to 99999

ULSI (Ultra Large Scale Integration) introduced in 1984, having transistor 1000000 and more and logic gates 100000 and more

WSI (Wafer Scale Integration) is a means of building very large integrated circuits that uses an entire silicon wafer to produce a single "super-chip".

SoC or SOC (System On Chip) is an integrated circuit in which all the components needed for a computer or other system are included on a single chip.

3D-IC (3 Dimensional Integrated Circuit) has two or more layers of active electronic components that are integrated both vertically and horizontally into a single circuit.

Name	Signification	Year	Transistors number	Logic Gates number
SSI	small-scale integration	1964	1 to 10	1 to 12
MSI	medium-scale integration	1968	10 to 500	13 to 99
LSI	large-scale integration	1971	500 to 20 000	100 to 9999
VLSI	very large-scale integration	1980	20 000 to 1 000 000	10 000 to 99 999
ULSI	ultra-large-scale integration	1984	1 000 000 and more	100 000 and more

Companies works in VLSI

Today, VLSI jobs are one of the highly paid occupation of the world, I have tried to figure out some of the companies which are working in VLSI domain. If you are interested in physical design send your resume at  vlsijunction@gmail.com

1. AMD
2. Aricent
3. Alten
4. Altran
5. Analog Devices (India) Pvt. Ltd. 
6. Blackpepper 
7. BLR Labs
8. Broadcom India 
9. Cisco
10. Cypress Semiconductors
11. Cyient
12. einfochip
13. Global Foundries
14. Graphene Semiconductors
15. HCL Technologies India Pvt. Ltd.
16. IBM
17. Infineon Technologies India Pvt. Ltd.
18. Intel
19. Invecas
20. Microsemi
21. mirafra
22. Mindlance
23. MosChip Semiconductor Technology Ltd.
24. Sasken Communications Technologies Ltd.
25. Sankalp Semiconductors
26. ST Microelectronics Ltd.
27. Tata Elxsi
28. Texas Instruments (India) Ltd.
29. Wipro Ltd.
30. Whizchip
31. Xilinx        

and Many More companies are there......

Routing

Routing Concept In Physical Design

After the floorplanning and placement steps in the design, routing needs to be done. Routing is nothing but connecting the various blocks in the chip with one another. Until now, the blocks were only just placed on the chip. Routing also is spilt into two steps

1. Global Routing:

It basically plans the overall connections between all the blocks and the nets. Its main aim is to minimize the total interconnect length, minimize the critical path delay. It determines the track assignments for each interconnect.

a. The chip is divided into small blocks. These small blocks are called routing bins. The size of the routing bin depends on the algorithm the tool uses. Each routing bin is also called a gcell. The size of this gcell depends on the tool.Each gcell has a finite number of horizontal and vertical tracks. Global routing assigns nets to specific gcells but it does not define the specific tracks for each of them. The global router connects two different gcells from the centre point of each gcell.

b. Track Assignment: The Global router keeps track of how many interconnections are going in each of direction. This is nothing but the routing demand. The number of routing layers that are available depend on the design and also, if the die size is more, the greater the routing tracks. Each routing layer has a minimum width spacing rule, and its own routing capacity. For Example: For a 5 metal layer design, if Metal 1, 4, 5 are partially up for inter-cell connections, pin, VDD, VSS connections, the only layers which are routable 100% are Metal2 and Metal3. So if the routing demand goes over the routing supply, it causes Congestion. Congestion leads to DRC errors and slow runtime

2. Detailed Routing:

In this step, the actual connection between all the nets takes place. It creates the actual via and metal connections. The main objective of detailed routing is to minimize the total area, wire length, delay in the critical paths. It specifies the specific tracks for the interconnection; each layer has its own routing grid, rules. During the final routing, the width, layer, and exact location of the interconnection are decided.After detailed routing is complete, the exact length and the position of each interconnect for every net in the design is known. The parasitic capacitance, resistance can now is extracted to determine the actual delays in the design. The parasitic extraction is done by extraction tools. This information is back annotated and the timing of the design is now calculated using the actual delays by the Static Timing Analysis Tool. After timing is met and all other verification is performed such as LVS, etc, the design is sent to the foundry to manufacture the chip.

Frequently Asked Question in Physical Design Interviews

Click here for more questions

Questions                                                                                       Next Page

1. Tell me about your project experience?
2. What are technology node you worked on?
3. How Many Tape out you did? 
4. which customer/client you have worked with?

Questions Based on Floor Planning

1. What all checks you will perform before starting floor planning?
2. What are inputs given to the floor planning stage?
3. What kind of blockages you have given to your last project?
4. How you will determine the distance between two macros?
5. what is the size of your block?
6. what are general guidelines you followed for Macro placement?
7. How many macros and standard cell were there in your block?
8. how will you place macro?
9. In your design memories are there but not connected anywhere, where you will place the memory?
10. if your design is 8 layer and your block is 4 layer, how will you place.

Question Based on Placement and Route

1. How many blockages are there in your design, how will you solve blockages
2. whether routing is possible in HALO
3. How will you solve routing congestion
4. How many type of congestion were there in your design
5. How will you find the distance between two macros
6. how you use to do routing
7. How will you solve the congestion when utilization and cell density is more?

Question Based on STA & CTS

1. What is goal of CTS?
2. What are inputs to CTS?
3. What is the target skew?
4. what are inputs you have given in CTS
5. how will you solve setup violation
6. what is hold, how will you solve it
7. suppose your design is of 500 mhz frequency, setup and hold are fix. If frequency is increased to 750 mhz, what will happen to setup and hold
8. how will you build clock tree, describe the procedure
9. what is slew, what is relation between transition and slew
10. how you use to do cts
11. what is virtual clock
12. how will you save time in cts optimizations
13. what are false path
14. How signal integrity impact setup and hold violation?
15. How to fix setup and hold violation after p & r?

Question Based on Physical Verfication

1. what are the files getting evaluated during LVS stage

Miscellaneous Questions

 For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select and Why?
What is partial floor plan?  
 What are the steps that you have done in the design flow?What are the issues in floor plan?
How can you estimate area of block?
How much aspect ratio should be kept (or have you kept) a
what is the utilization?
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
 
After adding stripes also if you have hot spot what to do?
What is threshold voltage? How it affect timing?
What is content of lib, lef, sdc? 
What is meant by 9 track, 12 track standard cells?
What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
What is setup Time and hold time? Why there are ? What if setup Violates and hold violates?In a circuit, for reg to reg path ...
Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
How R and C values are affecting time?How ohm (R), fared (C) is related to second (T)?What is transition? 
What if transition time is more?
What is difference between normal buffer and clock buffer?
What is antenna effect?
 What is ESD?
What is cross talk? How can you avoid?
How double spacing will avoid cross talk?
What is difference between HFN synthesis and CTS?What is hold problem? How can you avoid it?
What are the steps that you have done in the design flow?What are the issues in floor plan?
How can you estimate area of block?How much aspect ratio should be kept (or have you kept) and 
what is the utilization?How to calculate core ring and stripe widths?What if hot spot found in some area of block? 
How you tackle this?After adding stripes also if you have hot spot what to do?What is threshold voltage? 
What are DFM issues? What is the difference between synthesis and simulation?What is metal density
 metal slotting rule?What is OPC, PSM?Why clock is not synthesized in DC?What are high-Vt and low-Vt cells?
What corner cells contains?What is the difference between core filler cells and metal fillers?
How to decide number of pads in chip level design?What is tie-high and tie-low cells and where it is used?
What is DEF?
What are the steps involved in designing an optimal pad ring?
What is grided and gridless routing?What is a macro and standard cell?What is congestion?
Whether congestion is related to placement or routing?What are clock trees?What are clock tree types?
Which layer is used for clock routing and why?What is cloning and buffering?What are placement blockages?
How slow and fast transition at inputs effect timing for gates?
What is antenna effect?
What is logic optimization and give some methods of logic optimization.What is the significance of negative slack?
What is signal integrity? How it affects Timing?
What is IR drop? How to avoid .how it affects timing?
What is EM and it effects?
What is a grid .why we need and different types of grids?
What is core and how u will decide w/h ratio for core?What is effective utilization and chip utilization?What is latency?
 Give the types?How the width of metal and number of straps calculated for power and ground?What is negative slack ?
 How it affects timing?What is track assignment?
In which layer do you prefer for clock routing and why?If in
your design has reset pin, then it’ll affect input pin or output pin or both?
 During power analysis, if you are facing IR drop problem, then how did u avoid?Define antenna problem and
 how did u resolve these problem?How delays vary with different PVT conditions? Show the graph.Explain the flow of physical design
 and inputs and outputs for each step in flow.What is cell delay and net delay?What are delay models and what is the difference
 between them?What is wire load model?What does SDC constraints has?
Differentiate between a Hierarchical Design and flat design?Which is more complicated when u have a 48 MHz and 500 MHz clock design?
Name few tools which you used for physical verification?What are the input files will you give for primetime correlation?
What are the algorithms used while routing? Will it optimize wire length?How will you decide the Pin location in block level 
design?If the routing congestion exists between two macros, then what will you do?How will you place the macros?How will you
 decide the die size?If lengthy metal layer is connected to diffusion and poly, then which one will affect by antennaproblem?
If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using7LM?
In your project what is die size, number of metal layers, technology, foundry, number of clocks?
How many macros in your design?What is each macro size and no. of standard cell count?
How did u handle the Clock in your design?
What are the Input needs for your design?
What is SDC constraint file contains?How did you do power planning?How to find total chip power?How to calculate core ring width, macro ring width and strap or trunk width?How to find number of power pad and IO power pads?What are the problems faced related to timing?
How did u resolve the setup and hold problem?
What is signal integrity? How it affects Timing?* 
 What are types of routing?
What is core and how u will decide w/h ratio for core?* What is effective utilization and chip utilization?
What is latency? Give the types?
What are the steps involved in designing an optimal pad ring?
What are the steps that you have done in the design flow?
What are the issues in floor plan?
How much aspect ratio should be kept (or have you kept) and what is the utilization?*
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
After adding stripes also if you have hot spot what to do?
Why higher metal layers are preferred for Vdd and Vss?
What are clock tree types?H tree, Balanced tree, X tree, Clustering tree, Fish bone
What is cloning and buffering?
Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating thecell.Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease thedealy.What parameters (or aspects) differentiate Chip Design & Block level design??


How do you place macros in a full chip design?
What are inputs for Star RC extraction.
inputs for PT (how it works and what format you take design)
how congestion you check what what was the ration, and how you fixed
What happen if you have insertion delay (apart for timing violation)
Floor planning, why we need .lib for floorplaning (apart from the power info)
Explain PD flow
how CLKBUF is differentiating with normal buffer, what if we use normal buffer.
latch up internal structure
why endcap, internal structure and how u differentiate with filler cell
What are all inputs u need for floorplan ?
What are the information present in LEF file?
What is END CAP cells ?
Why we check hold for fast fast corner ?
At which edge we will check setup and hold ?
if in case u havent provided lef then what will u do ?
What is useful skew?
what is DECAP cells ?
What are the steps for fixing setup and hold violations?
What is antenna violation how will u fix it ?
In antenna violation fixing why we are going for higher layers in metal jogging?
What maximum skew u used in your design ?
What is your insertion delay in that case ?
What is clk buffer and normal delay buffer?
What will you do if a path has  both setup and hold violations?
What is false path and multi cycle path?
what is LVT HVT SVT cells ?
How big was your previous design..?(Expectation was block size and gate count )
Hands on experience on PnR tools.
What were the challenges faced in your design and how did you overcome.?
How do you use the blockage technique effectively to reduce congestion.?
What are the types of blockages.?
Challenges in 28nm Technology.
How to fix Setup and Hold fixes..?
Buffer insertion technique, how the setup and hold varies with the buffer location(between source and destination)
What is antenna effect and the measures taken to over come.
Explain useful Skew technique
what type of challenges u faced in your design?
 what are the drastically changes come when u move from 180 nm to 28nm?
What is NDR? 
what are the timing challenges u faced in ur design. and how did u fixed?
what is Antenna effect. how do u fix. 
which tool u used for sign off.
how can you resolve EM issues in your design.
what is tap cell. why we use it.
Explain latchup effect
IF u face congestion in ur design during routing stage. how will u fix it. 
what are the inputs of red hawk.




Click here for more questions

List of Topics

Topics                                                                             Date of Last Update

1. Floor Planning .......................................................................      22 Aug 2015
2. Power Planning  .....................................................................      7 Aug 2015
3.  Placement ...............................................................................     8 Aug 2015
4.  Clock Tree Synthesis ..............................................................     8 Aug 2015
5.  Routing ...................................................................................     8 Aug 2015
6.  Static Timing Analysis ...........................................................      8 Aug 2015
7.  Physical Verification ..............................................................      8 Aug 2015
8.  Impotant Input Files ...............................................................      6 Aug 2015
9.  IC Compiler Tutorial ..............................................................     15 Aug 2015
10.  Physical Design Flow ...........................................................   19 Aug 2015
11.  Types of cells used in Physical Design ................................    20 Aug 2015
12.  Basics of Linux Commands .................................................     21 Aug 2015
13.  Double patterning..................................................................    22 Aug 2015
14.  Advance Onchip variations (AOCV) ......................................    22 Aug 2015
15.  Statistical Static timing Analysis .............................................    18 Sep 2015
16.  Sanity Checks .........................................................................   7 Oct 2015
17.  Signal integrity in ASIC ...........................................................   7 Oct 2015
18.  Interview Questions .................................................................  17 Oct 2015
19.  Non Default Rules (NDR Rules) ...............................................  17 Oct 2015
20.  Antennae Effects .......................................................................  17 Oct 2015
21.  Crosstalk ....................................................................................  17Oct 2015
22.  DEF files ....................................................................................  17Oct 2015
23. LEF files ....................................................................................   17Oct 2015
24. Low Power Design Techniques
25. CMOS Fundamentals
26. Interview Questions

List of Topics Coming Soon

1. Checks need to be done before each steps
2. Latch Up Effect
3. Electrostatic Discharge (ESD)
4. Basics of DFT
5. Basics of Synthesis
6. Advance STA concepts