Automatic Test Pattern Generation (ATPG)

What is ATPG ?

 

ATPG stands for Automatic Test Pattern Generation. It is a DFT (Design for Testability) technique used to create test patterns that can detect manufacturing defects in an integrated circuit (IC).

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What Does ATPG Do?

ATPG tools analyze the gate-level netlist of a chip and generate test vectors (input patterns and expected outputs) to:

• Detect stuck-at faults (e.g., a net stuck at 0 or 1)
• Detect transition delay faults
• Improve fault coverage for logic defects

These patterns are later applied using scan chains during testing on Automatic Test Equipment (ATE).

 

ATPG Flow in VLSI

1. DFT Insertion
• Add scan chains, test logic (e.g., muxed flip-flops), and test controllers.
2. Fault Modeling
• Define fault models like stuck-at, transition, path delay, bridging faults, etc.
3. Pattern Generation
• Generate input stimulus to propagate faults to observable outputs.
4. Pattern Compression (optional)
• Compress patterns to reduce test time and memory.
5. Test Coverage Analysis
• Check % of faults detected.
6. Pattern Export
• Export to a tester format (like STIL, WGL, or VCD).

Fault Models
Fault Type	Description
Stuck-at Faults	Signal stuck at 0 or 1 regardless of logic
Transition Faults	Detect slow-to-rise or slow-to-fall faults
Bridging Faults	Two signals are shorted
Path Delay Faults	Delay on a particular path

🔧 Tools Used

·       Popular ATPG tools include:

·       Synopsys TetraMAX / TetraMAX II

·       Mentor Tessent

·       Cadence Modus

 

📊 Why ATPG is Important

·       Increases manufacturing test quality

·       Helps detect defective chips before packaging

·       Achieves high fault coverage (~99% for stuck-at)

·       Reduces field failure rates