Monday, 23 December 2019

Question which were asked on 22nd dec session (doubts clearing session)

  1. Difference between flat and hierarchical design?
  2. What is the need for sanity checks at floorplan stage?
  3. Explanation of flipchip?
  4. How can we decide no of routing layers in a design? Does more no of routing layers beneficial.
  5. Difference between drive strength and fanout.
  6. For specific corner can a path have both setup and hold violation?
  7. Why do we have no of routing layers better or worse?
  8. What is functional ECO?
  9. Difference SDC file as an input to floor planning although we don’t do timing analysis after floor planning?
  10. How to decide max transition on clock and data?
  11. What is RDL layer?
  12. Two clock paths coming from same PLL will always be synchronous or asynchronous? Or are there different conditions attached to it.
  13. Why do we need driving cell for input ports and load for the output ports?
  14. Is there any difference between tie cells and level shifters?
  15. Why setup is only considered for worst case? and Hold for best case? and What will happen if reverse is done?
  16. Explanation regarding capture and launch clock.
  17. Difference between HFNS and CTS.  
  18. how std cells are placed? With complete explanation?
  19. how to resolve unsigned nets in the synthesis stage?
  20. how to resolve max tran and max cap vailotions?
  21. implicite and explicit exceptions in cts stage?
  22. Input files based on Physical Design (Indeep and explain with those files?
  23. Synchronizer Logic With Example?
  24. Frequency divider for 3,4,5,6,7,8?
  25. When we ar eworking  90nm or other tech  how to change  one technology to another technology or else for given technology is fixed we can't  change for a same project
  26. how to fix drc
  27. is drc and crpr related