Sunday, 30 August 2015

Blockages

BLOCKAGES
Placement blockages prevent the placement engine from placing cells at specific locations. Routing blockages block routing resources on one or more layers and it can be created at any point in a design flow. In general placement blockages are created at floor planning stage and routing blockages are created before using any routers. It acts like guidelines for placement of standard cells. Blockages will not be guiding the tool to place the standard cells at some particular area, but it won’t allow the tool to place the standard cell in the blocked areas (in both placement and routing blockages). This is how the blockages acts like guidelines for standard cell placement. During the CTS process (Clock Tree Synthesis) in order to balance the skew, more number of buffers and inverters are added and blockages are used to reserve space for buffers and inverters.

Placement blockages

Use placement blockages to:
  • Define std-cells and macro area
  • Reserve channels for buffer insertion
  • Prevent cells from being placed at or near macros
  • Prevent congestion near macros

Soft (Non buffer blockage)

  • Only buffers can be placed and standard cells cannot be placed.

Hard (Std-cell blockage)

Blocks all std-cells and buffers to be placed. Std-cell blockages are mostly used to:
  • Avoid routing congestion at macro corners
  • Restrict std-cells to certain regions in the design
  • Control power rails generation at macro cells

Partial blockages

By default a placement blockage has a blockage factor of 100%. No cells can be placed in that area, but flexibility of blockages can be chosen by partial blockages. To reduce placement density without blocking 100% of the area, changing the blockage factor of an existing blockage to lower value will be a better option.

Keepout Margin (Halo)


                                                            fig-1: Halo
  • It’s the region around the boundary of fixed macros in design in which no other macros or std-cells can be placed. It allows placement of buffers and inverters in its area. Pictorial representation of halo is mentioned in the figure-1.
  • Halos of adjacent macros can overlap; there the size of halo determines the default top level channel size between macros. Prevent cells from being placed at or near the macros.
  • If the macros are moved from one place to another, hallows will also be moved.

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