Purpose and contents of the different scripts
The purpose of this file is to handoff a floorplanned CEL to the next step, which is the place_opt step. Depending on the input format (MW, Verilog, DDC), it will read the appropriate files and also include the floorplan information provided via either a DEF input file, or already existing in the initial floorplanned CEL.
If the input format is MW CEL, then no SDC constraints are loaded because they are assumed to be in the CEL already. The same is the case when loading DDC. It is only in the case of loading a verilog netlist, that the read_sdc command is executed.
We strongly recommend the usage of group paths to differentiate the Input-to-flop, Flop-to-Output and input-to-outputs feed through paths. That will improve the visibility during optimization. Just like with the SDC constraints, we will not create the group paths in case we enter with a MW cel or a DDC, but only in the case of entering with a pure ASIC flow, i.e. Verilog + sdc constraints.
If certain floorplan constraints need to be added (such as placement or routing blockages), it is recommended to do this in this file, after the read-DEF section.
This file is also setting up the different MV and MCMM portions.
The output CEL created by this script is called: init_design_icc.
The purpose of this script is to execute the placement and the placement based optimization. The default command that is executed is:
place_opt -area_recovery -effort low
That will provide the fastest result with still good QoR. After reading the initial CEL, created in the previous step, a file called icc_scripts/common_optimization_settings_icc.tcl It is sourced. That file contains several settings that are recommended to be used during each of the optimization steps that follow. Because we also have the capability to execute a place_opt -cts, Which will also create the clock tree, it is required to also include the icc_scripts / common_cts_settings_icc.tcl file. That file specifies any clock tree related settings.
In addition to the default place_opt command mentioned above, the script contains several other flavors of the
place_opt flow. These steps are put in comments and detailed explanation is provided for each of them. It is sufficient to comment out the undesired place_opt command, and uncomment the desired one.
Eg if the user wants to run scan chain reordering in place_opt, he has to put comments before the default place_opt command, and uncomment the following lines:
## What commands do you need when you want to optimize SCAN?
# Read_def $ ICC_IN_SCAN_DEF_FILE
# Redirect -file $ REPORTS_DIR / scan_chain_pre_ordering.rpt
# Place_opt -area_recovery -optimize_dft -num_cpus $ ICC_NUM_CPUS
The output CEL created in this step is called place_opt_icc.
The purpose of this script is to execute the following three steps:
•Clock tree synthesis and clock tree optimization (CTO)
•Optimization of the post-cts design, including hold fixing based on virtual routes
•Routing of the clock tree
The file icc_scripts / common_cts_settings_icc.tcl needs to be edited when you want to define any clock tree specific requirements.
•Clock tree exceptions.
•Non Default Routs (NDR's) to define e.g. double spacing for Xtalk avoidance on clock nets.
•Definition of clock tree master cells, for clock tree synthesis, or delay insertion during clock tree optimization (CTO).
•Inter clock delay balancing options specified via set_inter_clock_delay_options.
By default, ICC-RM does not execute any of these clock tree settings, because these are obviously very design dependent.
In the clock_opt_icc.tcl script itself, there are 3 variants of the default clock_opt flow provided:
•How to execute inter clock delay balancing?
•How to update the IO-latency after CTS?
•What commands to execute once your design becomes too congested after clock tree synthesis?
The cell that is saved at the end is called clock_opt_icc
The purpose of this script is to execute the routing step and proceed with the post route optimization in order to close the design for timing, DRC, and other design constraints.
The command that is executed is the mainstream route_opt command, ie:
•route_opt -effort low -xtalk_reduction
The tool will run by default in Xtalk Delta Delay (XDD) mode.
To enable static noise (aka glitches), as well as some advanced timing analysis capabilities (Arnoldi, timing windows, CRPR) you will have to edit the file:
./icc_scripts/common_route_si_settings.tcl and uncomment the appropriate lines.
The route_opt_icc.tcl scripts also contains (in comments), the required commands to run leakage power optimization, as well as some of the frequent used variants of route_opt:
•Incremental route_opt optimization
•Limiting the potential disturbance to the design using -size_only
•Hold fixing only optimization
The cell that is saved at the end is called route_opt_icc
The purpose of this script is to provide the commands to execute the following chip finishing steps:
• Antenna fixing against the plasma effect.
•Critical area reduction by executing timing driven detail route wire spreading ( Global route wire spreading is on by default as part of the Xtalk avoidance).
•Redundant via insertion.
•Standard cell filling.
•Timing driven Metal filling.
None of these steps are enabled by default, but can be controlled easily by editing the chipfinishing variables in the
The cell that is saved at the end is called chip_finish_icc
This TCL script is opening the chipfinished cell, and executes run_signoff and signoff_opt.
The run_signoff command is running Synopsys's signoff extraction tools: Star-rcxt and Primetime. The ICC database in annotated with these signoff numbers.
The signoff_opt command is optimizing the design by making use of these signoff delays. After every optimization loop, the design will be incrementally extracted by Star-rcxt and incrementally timed by PTSI. With this methodology, the output is a design that is signoff ready.
This step is run by default after chipfinishing. If that step include metal filler, the signoff_opt_icc.tcl will also execute the required trim_eco_filler commands to clean up some of the modified filler polygons.
The purpose of this script is to create several output files that will allow you to proceed with the next steps of the flow.
Following files are generated:
•Verilog netlist with and without PG connections
•SBPF binary parasitic file (ASCII SPEF command is commented out)
•GDSII streamout file