Friday 7 August 2015

Floor Planning

Introduction To Floor Planning

This is the first major step in getting your layout done, and this is the most important one.Your floorplan determines your chip quality. Floorplanning includes
  1. Define the size of your chip/block and Aspect ratio
  2. Defining the core area and IO core spacing
  3. Defining ports specified by top level engineer.
  4. Design a Floor Plan and Power Network with horizontal metal layer such that the total IR Drop must be less than 5% (VDD+VSS) of VDD to operate within the power budget.
  5. IO Placement/Pin placement
  6. Allocates power routing resources
  7. Place the hard macros (fly-line analysis) and reserve space for standard cells. (Please refer rules for placing hard macros)
  8. Defining Placement and Routing blockages blockages
  9. If we have multi height cells in the reference library separate placement rows have to be provided for two different unit tiles.
  10. Creating I/O Rings
  11. Creating the Pad Ring for the Chip
  12. Creating I/O Pin Rings for Blocks                                                                                                                                                                                                                                                                                                                                                                    Every subsequent stage like placement, routing and timing closure is dependent on how good your foorplan is. In a real time design, you go through many iterations before you arrive at an optimum floorplan.

Floorplanning takes in some of the geometrical constraints in a design. Examples of this are:
  • Bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip.
  • Line drivers often have to be located as close to bonding pads as possible.
  • Chip area is therefore in some cases given a minimum area in order to fit in the required number of pads.
  • Areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit.
  • Purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks.
  • Some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.

Inputs for Floor Planning Stage

  1. Synthesized Netlist (.v, .vhdl)
  2. Logical and Physical Libraries
  3. TLU+ Files
  4. Physical partitioning information of the design
  5. Design Constrains (SDC)
  6. Physical information of your design (rules for targeted technology)
  7. Floorplan parameters like height, width, utilization, aspect ratio etc.
  8. Pin/pad Position

Outputs of Floor Planning Stage

  • Die/Block area
  • I/O pad/placed
  • Macro placed
  • Power grid design
  • Power pre-routing
  • Standard cell placement areas.

Purpose of Floor Planning

   The first step in the Physical Design flow is Floor Planning. Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.

    Based on the area of the design and the hierarchy, a suitable floorplan is decided upon. Floor Planning takes into account the macro's used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Floor planning also decides the IO structure, aspect ratio of the design. A bad floor-plan will lead to waste-age of die area and routing congestion.

    In many design methodologies, Area and Speed are considered to be things that should be traded off against each other. The reason this is so is probably because there are limited routing resources, and the more routing resources that are used, the slower the design will operate. Optimizing for minimum area allows the design to use fewer resources, but also allows the sections of the design to be closer together. This leads to shorter interconnect distances, less routing resources to be used, faster end-to-end signal paths, and even faster and more consistent place and route times. Done correctly , there are no negatives to Floor-planning.
As a general rule, data-path sections benefit most from Floorplanning, and random logic, state machines, and other non-structured logic can safely be left to the placer section of the place and route software.

    Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits. Example structures that make up data paths are Adders, Subtractors, Counters, Registers, and Muxes.

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  1. Hello,
    How do we calculate the IO to core spacing. Please provide the info in detail with all the calculations required.

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