Monday 24 August 2015

Signal Integrity

Signal integrity 
Signal Integrity is the ability of an electrical signal to carry information reliably and to resist the effects of high-frequency electromagnetic interference from nearby signals. Effects: CrossTalk, EM, Antennae Effects.


Switching of the signal in one net can interference neighboring net due to cross coupling capacitance. This affect is known as cross talk. Crosstalk can lead to crosstalk-induced delay changes or static noise.

Techniques to solve Crosstalk

Double spacing   =>  more spacing=>less capacitance=>less cross talk
Multiple vias       =>  less resistance=>less RC delay
Shielding             =>  constant cross coupling capacitance =>known value of crosstalk
Buffer insertion   =>  boost the victim strength.
Net ordering        =>  in same metal layer change the net path.
Layer assignment=>  Change the metal layer of two nets if possible. (One s/g in mtl3 and one signal in 4).

• Signal Electro Migration

Electromigration is the permanent physical movement of metal in thin wire connections resulting from the displacement of metal ions by flowing electrons. ectromigration can lead to shorts and opens in wire connections, causing functional failure of the IC device.
High current densities cause wearing of metal due to EM.

Techniques to solve EM:

1) Increase the width of the wire

2) Buffer insertion

3) Upsize the driver

4) Switch the net to higher metal layer

Antennae effects

The antenna effect [plasma induced gate oxide damage] is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. The IC fabs normally supply antenna rules that must be obeyed to avoid this problem and violation of such rules is called an antenna violation. The real problem here is the collection of charge.

A net in an IC will have atleast one driver (which must contain a source or drain diffusion or in newer technology implantation is used), and at least one receiver (which will consist of a gate electrode over a thin gate dielectric). Since the gate dielectric is very thin, the layer will breakdown if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide. But during the construction phase, if the voltage is build up to the breakdown level when not protected by this diode, the gate oxide will breakdown.

Antenna rules are normally expressed as an allowable ratio of metal area to gate area. There is one such ratio for each interconnect layer. Each oxide will have different rule.

Antenna violations must be fixed by the router. Connecting gate oxide to the highest metal layer, adding vias to near the gate oxide to connect to highest layers used and adding diode to the net near the gate are some fixes that can be applied. Adding diode rises the capacitance and makes circuit slower and consumes more power.

Techniques to solve Antennae violation

1. Jumper insertion
2. Diode insertion near logic gate input pin
3. Buffer Insertion


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