## Tuesday 10 November 2015

### Dynamic Power Dissipation

#### Charging and discharging of load capacitance

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore in one complete charge/discharge cycle, a total of Q=CLVDD is thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: $P = 0.5 C V^2 f$.
Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor $\alpha$, called the activity factor. Now, the dynamic power dissipation may be re-written as $P = \alpha C V^2 f$.
A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1. If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.