As all of us knows fanout of the clock signal is high. Apart from that few of the signals are existed in design like reset ,clear and scan enable signals and etc..
The signal nets which have more fanout compared to specified fanout is also known as HFN
we all know that
set_max_fanout <some number> during synthesis this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net.
Why do we do this ?
As we understanding HFN has lot of load obviously it has huge capacitance.
And if we tried to report the timing it reports very huge cap violations and huge delays in the timing path.
So to avoid this huge delays in timing path we are setting the same net as HFN.
another way to set an HFN to synthesis tool: set_ideal_net <net name>
This way the synthesis tool knows the specified net as a high fanout net and does not buffer them .