- Explain concept of cross talk?
- How can you overcome cross talk problem?
- what is shielding? how it avoid avoids crosstalk problem?
- how spacing h reducing crosstalk noise?
- Why double spacing and multiple vias are used related to clock?
- where do you insert buffer to avoid crosstalk? how buffer insertion solve the problem?
- Difference between Chip Design and Block level design?
- What are the ways to place macros in a full chip design?
- what are the differences between Hierarchical Design and flat design?
- Why 500 MHz clock design is complex than 48Mhz design?
- What all tools used in physical verification?
- what are the inputs you will give in physical verification
- how will you solve the congestion between two macros?
- what all parameters you will consider while estimating die size?
- What is each macro size and number of standard cell count?
- Depends on your design.
- What are the input needs for your design?
- What does SDC (Synopsys design contraint) file contains?
- how will give Clock definitions ?
- what are timing Timing exception, how will you constraint them?
- what is Input and Output delays, what are prime time commands for it?
- How did you do power planning?
- Explain, how will you find number of power pad and IO power pads?
- How the number of power straps calculate?
- How to find total power of chip, What are the problems you can faced with respect to timing?
- what is setup and hold problem, how will you solve it?
- which is preferable layer for clock routing and why?
- what do you mean by IR drop problem, how will you overcome by this problem?
- what is antenna effect, how does it impact the and how would you resolve antennae effect problem?
- How are the PVT conditions? Describe using graph?
- Describe the physical design flow?
- what all the and inputs and outputs for each step of physical design?
- What is cell delay and net delay, how will you reduce this delays?
- What are the different timing delay models available?
- What is wire load model (WLM)?
- Why higher metal layers are preferred for power?
- What do you mean by logic optimization techniques, how it will work?
- what is slack, how will you calculate slack?
- what are the parameters on which slack depends on?
- What do you mean by of negative slack, how will u make it positive?
- What is EM and it effects?
- What are types of routing ?
- What do you mean by clock latency? what are the types of clock latecies?
- What is track assignment in routing stage?
Saturday, 20 February 2016
Physical Design Interview Question Part 1
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Tks very much for your post.
ReplyDeleteAvoid surprises — interviews need preparation. Some questions come up time and time again — usually about you, your experience and the job itself. We've gathered together the most common questions so you can get your preparation off to a flying start.
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