- How many blocks/chips designed in your total years of Experience?
- What is the latest project you finished? Was it block/full-chip?
- What is the design application?
- Input is RTL or gate level netlist?
- Explain Netlist(or RTL)-gdsii flow?
- What are the input needs for your design?
- In which field are you interested?
- What is the most challenging task you handled?
- What is the most challenging job in P&R flow?
- What parameters (or aspects) differentiate Chip Design and Block level design?
- List down difference between a flat and hierarchical design?
- What is the difference between soft macro and hard macro?
- What are the challenges seen as technology shrinks?
- What scan techniques being used?
- Experience with timing closure & congestion issues?
- Any experience with ECO (functional or timing ECO).
- what are issues you face during tapeout time?
- If you have shifted from one tool to another one, how long did it take to ramp up
- on the new tool?
- What is the difference between a latch and a flip-flop?
- what all the parameters on which clock frequency depends in design?
- Define threshold voltage?
- How do you size NMOS and PMOS transistors to increase the threshold voltage?
- how threshold voltage is dependent on temperature?
- What is the effect of gate voltage on mobility?
- What is the effect of temperature on mobility?
- Design a circuit to divide input frequency by 2?
Saturday, 20 February 2016
Physical Design Interview Question Part 2
Posted by Akshay at 22:05