Saturday 20 February 2016

Physical Design Interview Question Part 2

  1. How many blocks/chips designed in your total years of Experience?
  2. What is the latest project you finished? Was it block/full-chip?
  3. What is the design application?
  4. Input is RTL or gate level netlist?
  5. Explain Netlist(or RTL)-gdsii flow?
  6. What are the input needs for your design? 
  7. In which field are you interested? 
  8. What is the most challenging task you handled? 
  9. What is the most challenging job in P&R flow?
  10. What parameters (or aspects) differentiate Chip Design and Block level design? 
  11. List down difference between a flat and hierarchical design? 
  12. What is the difference between soft macro and hard macro?
  13. What are the challenges seen as technology shrinks?
  14. What scan techniques being used?
  15. Experience with timing closure & congestion issues?
  16. Any experience with ECO (functional or timing ECO).
  17. what are issues you face during tapeout time?
  18. If you have shifted from one tool to another one, how long did it take to ramp up 
  19. on the new tool?
  20. What is the difference between a latch and a flip-flop?
  21. what all the parameters on which clock frequency depends in design?
  22. Define threshold voltage? 
  23. How do you size NMOS and PMOS transistors to increase the threshold voltage? 
  24. how threshold voltage is dependent on temperature? 
  25. What is the effect of gate voltage on mobility? 
  26. What is the effect of temperature on mobility? 
  27. Design a circuit to divide input frequency by 2?

No comments:

Post a Comment