Sunday, 28 February 2016

Physical Design Interview Question Part 3

1. How many blocks/chips designed in your total years of Experience?

2. What is the latest project you finished? Was it block level implementation or full-chip implementation?

3. What is the design application?

4. Input is RTL or gate level netlist?

5. Explain Netlist(or RTL)-gdsii flow?

6. What are the input needs for your design? 

7. In which field are you interested? 

8. What is the most challenging task you handled? 

9. What are the challenges you faced in P&R flow? 

10. What parameters (or aspects) differentiate Chip Design and Block level design? 

12. Differentiate between a Hierarchical Design and flat design? 

13. What is the difference between soft macro and hard macro?

14. What are Ips?

15. What are the challenges you will see in lower technology?

16. What scan techniques being used?

17. Experience with timing closure & congestion issues?

18. Any experience with ECO (functional or timing ECO).

19. Towards the end of the project, what are some of the issues that can pop up , and 

20. how can they be fixed?

21. If you have shifted from one tool to another one, how long did it take to ramp up 

on the new tool?

22. What is the difference between a latch and a flip-flop?

23. On what basis we decide the clock frequency in any design?

24. Define threshold voltage? 

25. How does the size PMOS & NMOS transistors increases the threshold voltage? 

26.What is the effect of temperature on threshold voltage? 

27.What is the effect of gate voltage on mobility? 

28. What is the effect of temperature on mobility? 

29. If  we invert o/p of D flip-flop in the ip how does it will behave?

30.Design a circuit to divide input frequency by 2?

31. What is the maximum drive strength of standard buffers and inverters are available in your design? 

32. Why we increase the size and strength of inverters in buffer design? What will happen if you user inverter or buffer of maximum strength and size? 

33. What does lef and lib file contains?

34. What is generally in the x axis and y axis and what is linear line in any library(NLDM)?

35. What are the high speed and low speed cells?

36. What is the exact meaning of a capacitance?

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