Sunday 28 February 2016

Physical Design (Floorplanning) interview Question Part 4

1. Die size estimation:

2. How will you decide best floorplan? 

3. how to decide Aspect ratio? 

4.how to decide Macro placement ?

5. What is the target die size?

6.What is the expected utilization?

7. Does the area estimate include power/signal routing? 

8.What gates/mm2 has been assumed?

9.how to decide no. of routing layers?

10. Any special power routing requirements?

12. Please draw the overall floorplan ?

13. Is there an existing floorplan available in DEF? 

14. What are the number and type of macros (memory, PLL, etc.)?

15. Are there any analog blocks in the design? 

16. Placement of PLL? Analog placement requirements

17. Did you receive block size, pin locations from top level person?

18. How will you do floorplanning?(with out having data flow details)

19. How would you go about floorplanning when you have lots(hundreds) of macros?

20. What are the general guidelines to be followed when doing floorplanning?

21. how to decide Full chip IO ring: 

22. how to decide Total number of pins/pads and Location? 

23. how to decide Is the design pad limited? 

24. Number of digital I/O pins/pads?

25. Number of analog signal pins/pads? 

26. Number of power/ground pins/pads?

27. Will this chip use a wire bond/flipchip package? 

28. How IOSSO taken care? 

29. What ESD protection used for the IO ring? 

30. If flipchip, is it I/O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide?

4 comments:

  1. Will you please provide answers of above question because i am not able to get the answers.I will be very grateful if you provide me the solution.Thank you

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    2. Hi,

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      Thank You

      Delete
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