First of all, let us consider the sizing of an inverter. We have already seen that the propagation delay of the gate is proportional to (Rp + Rn)CL. The delay of an inverter can be minimized by keeping the output capacitance small or by decreasing the on resistance of the transistor. The CL consists of the diffusion capacitance of the transistors, the interconnect capacitance and the fan-out capacitance. Careful layout helps to reduce the diffusion and interconnect capacitances. The on-resistance of the transistor is inversely proportional to the W/L ratio of the device. It is known that the mobility of holes are approximately 2.5 times lower than that of electrons in Silicon. Thus, a 2.5 time wider PMOS transistor is needed to match its on-resistance to that of pull-down NMOS device. With such a sizing of NMOS and PMOS width, we can design an inverter with a symmetrical VTC (Voltage Transfer Characteristics) and equal high-to-low and low-to-high propagation delays. The diffusion capacitance is also increased with increasing widths and careful optimization is required.