Friday 29 November 2019

Basic Synthesis Flow

Logic Synthesis means converting RTL (Register Transfer Level) into logic gates with the help of synthesis tool. Design compiler by Synopys is an example of synthesis tool and it is one of the widely used tool across the industries. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.