- Difference between flat and hierarchical design?
- What is the need for sanity checks at floorplan stage?
- Explanation of flipchip?
- How can we decide no of routing layers in a design? Does more no of routing layers beneficial.
- Difference between drive strength and fanout.
- For specific corner can a path have both setup and hold violation?
- Why do we have no of routing layers better or worse?
- What is functional ECO?
- Difference SDC file as an input to floor planning although we don’t do timing analysis after floor planning?
- How to decide max transition on clock and data?
- What is RDL layer?
- Two clock paths coming from same PLL will always be synchronous or asynchronous? Or are there different conditions attached to it.
- Why do we need driving cell for input ports and load for the output ports?
- Is there any difference between tie cells and level shifters?
- Why setup is only considered for worst case? and Hold for best case? and What will happen if reverse is done?
- Explanation regarding capture and launch clock.
- Difference between HFNS and CTS.
- how std cells are placed? With complete explanation?
- how to resolve unsigned nets in the synthesis stage?
- how to resolve max tran and max cap vailotions?
- implicite and explicit exceptions in cts stage?
- Input files based on Physical Design (Indeep and explain with those files?
- Synchronizer Logic With Example?
- Frequency divider for 3,4,5,6,7,8?
- When we ar eworking 90nm or other tech how to change one technology to another technology or else for given technology is fixed we can't change for a same project
- how to fix drc
- is drc and crpr related
Monday, 23 December 2019
Question which were asked on 22nd dec session (doubts clearing session)
Posted by Akshay at 16:43