finFET seems to be the most promising and disruptive technology at the moment able to mantain the Moore’s Law trend and expectations. The most active players (IDM, Foundries, EDA companies and IP providers) in the semiconductor market are putting a lot of effort, investments and emphasis on this hot topic.
For this reason I decided to collect information and share a post regarding this technology. It’s not anymore the time for me to enter in mathematical and physical details, but my interest is to understand the reasons and the advantages of the FinFET technology from a marketing perspective.
The Moore’s Law and the market are pushing constantly to increase the density of transistors in chip and the performances in term of speed and power consumption. This scaling process seems to be at a technology limit for the planar transistor with length below 20nm: the electrical parameters start degrading and the silicon process variations impact heavily in the performances. The main reason of this degradation is due to the planar structure itself: the gate does not have a good electrostatic field control away from the surface of the channel. With geometry scaling, it brings to:
- Lower current in the channel
- Leakage current drain-source when the transistor is theoretically switched off
- Short channel effect
- High dependence on process variations (Vth and swing).
The solution seems to be indeed the 3D approach: the channel between source and drain is built as a three-dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped around the channel, so the gate can control the channel electrical field. In this structure, the gate can control much better the electrical field in the 3D channel.
Several options and enhancement are proposed. In the picture below a finFET has been built on SOI with a further reduction of current leakage. There can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.
FinFET technology impacts all the electrical parameters of the transistor and you have benefit in power consumption (static and dynamic), speed and voltage supply range. FinFETs also improve the always challenging tradeoff between performance and power: you can go faster with the same amount of power, compared to the planar equivalent, or save power at the same speed. In a list, the promised advantages over plan transistor:
- Higher drain current
- up to 37% switching speed
- Lower switching voltage
- less than half the dynamic power
- 90% less static leakage current
The above points reached with a low cost impact: leading foundries estimate the additional processing cost of 3D devices to be 2% to 5% higher than that of the corresponding Planar wafer fabrication.
State of the Art
Almost all the big players in the semiconductor eco-system are focusing on the finFET technology, so news, announcements and updates come out every day.
The finFET era started in 2011, when Intel unveiled the newfangled transistor technology at the 22nm node (now in production). Intel plans are to ramp up its second-generation finFET devices at 14nm by year’s end and move to 11nm by 2015.
Silicon Foundries are already defining their plans with finFETs technology. GlobalFoundries will deliver14nm finFET by 2014 and 10nm finFet by 2015. TSMC is planning to deliver 16nm finFET by 2014.
EDA player are dedicating big effort to model this complex device and to deliver compelling design tools to designers. In particular Synopsys is working hard to deliver tools and IP for FinFET design, as in the news.
Maybe we are at the beginning of a new era. finFETs can potentially determinate a big step forward in the never ending effort to reduce power consumption, to increase switching speed and number of transistors. Always with a cost reduction.