In some cases, signal takes too long transiting from one logic level to another, than a transition violation is caused. The Trans violation can be because of node resistance and capacitance.
- By upsizing the driver cell.
- Decreasing the net length by moving cells nearer (or) reducing long routed net.
- By adding Buffers.
- By increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation.