In this position, the individual will be responsible for driving Place-And-Route flow for Low Power Designs from netlist to GDS. Responsibilities will include complete ownership of sub chip PnR environment, clock tree design and driving Place-And-Route flow for full chip convergence and timing closer.
This position requires a Master’s Degree in Electrical Engineering or Computer Science with a minimum of 4 to 7 years of hands on experience in sub chip Place-And-Route flow with emphasis on 28nm and low power designs. Proficiency in SoC Encounter / Innovus / ICC / ICC II and experience in PERL/TCL/Shell scripting is a must.
The individual must have hands on experience with multiple low power hierarchical and flat ASICs at 28 nm and below nodes. Having exposure to Physical Verification flow for DRC and LVS closure for blocks is preferred. Ability to work with minimal supervision and drive to exceed expectations is a must. Good verbal and written communication skills are required.
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Job Location: Noida, Bangalore
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