• Tell me about yourself in brief
• Inputs to PNR
• Do you have knowledge on synthesis
• What are the validations and sanity checks you do on the outputs received from synthesis team
• Which file will you need to check if you see black box in the screen
• Which file you need to check if you see any floating pins and whom should you report in such case
• What does .tf file, .db file, .sdc file, .spef file .v files include
• What is floor plan and what is done as part of floor plan
• How do you fix placement of RAMs
• What is utilization factor and Area
• What is fly line analysis
• How do you decide the spacing between the macros and standard cells
• What are tie cells and can the size of array of tie cells be either increased or decreased? –No
• Which layers are preferred for power routing and why?
• Which is preferred to be the outer most layer or top layer
• What is the UF in floor plan
• What is the skew achieved in your project and what is the allowed skew
• What is local skew and global skew difference
• What are the tools used for PNR
• What is high fan out synthesis
• What is placement and what do we do in this step
• What is NLDM
• What is congestion and timing closure
• What special physical cells are used in your project
• Purpose of power domains, level shifter cells, isolation cells, Always on cell
• Where do we use Always On buffers
• How is drive strength and delay relation
• What is inversion temperature
• How is delay and temperature relation
• How is threshold voltage and temperature variations related
• What happens when you do congestion driven placement
• Where are the buffers placed? What is the functionality of buffers
• How do buffers speed up the signal in data or in clock even if it adds delay to the path
• What is set up and hold violation
• What are the ways to fix the set up violation
• Ways to fix hold violation
• What is STA and which tool is being used for STA
• What are the optimizations done in placement stage
• What are the power domains in your project
• What is switchable power domain
• Inputs to PNR
• Do you have knowledge on synthesis
• What are the validations and sanity checks you do on the outputs received from synthesis team
• Which file will you need to check if you see black box in the screen
• Which file you need to check if you see any floating pins and whom should you report in such case
• What does .tf file, .db file, .sdc file, .spef file .v files include
• What is floor plan and what is done as part of floor plan
• How do you fix placement of RAMs
• What is utilization factor and Area
• What is fly line analysis
• How do you decide the spacing between the macros and standard cells
• What are tie cells and can the size of array of tie cells be either increased or decreased? –No
• Which layers are preferred for power routing and why?
• Which is preferred to be the outer most layer or top layer
• What is the UF in floor plan
• What is the skew achieved in your project and what is the allowed skew
• What is local skew and global skew difference
• What are the tools used for PNR
• What is high fan out synthesis
• What is placement and what do we do in this step
• What is NLDM
• What is congestion and timing closure
• What special physical cells are used in your project
• Purpose of power domains, level shifter cells, isolation cells, Always on cell
• Where do we use Always On buffers
• How is drive strength and delay relation
• What is inversion temperature
• How is delay and temperature relation
• How is threshold voltage and temperature variations related
• What happens when you do congestion driven placement
• Where are the buffers placed? What is the functionality of buffers
• How do buffers speed up the signal in data or in clock even if it adds delay to the path
• What is set up and hold violation
• What are the ways to fix the set up violation
• Ways to fix hold violation
• What is STA and which tool is being used for STA
• What are the optimizations done in placement stage
• What are the power domains in your project
• What is switchable power domain
This is a good checkist. I recently had an interview. I used this for the preparation. I was happy to see that most of the questions I was asked were mentioned here.
ReplyDeleteReally
DeleteIEEE Project Domain management in software engineering is distinct from traditional project deveopment in that software projects have a unique lifecycle process that requires multiple rounds of testing, updating, and faculty feedback. A IEEE Domain project Final Year Projects for CSE system development life cycle is essentially a phased project model that defines the organizational constraints of a large-scale systems project. The methods used in a IEEE DOmain Project systems development life cycle strategy Project Centers in India provide clearly defined phases of work to plan, design, test, deploy, and maintain information systems.
ReplyDeleteThis is enough for me. I want to write software that anyone can use, and virtually everyone who has an internet connected device with a screen can use apps written in JavaScript. JavaScript Training in Chennai JavaScript was used for little more than mouse hover animations and little calculations to make static websites feel more interactive. Let’s assume 90% of all websites using JavaScript use it in a trivial way. That still leaves 150 million substantial JavaScript Training in Chennai JavaScript applications.