Friday, 17 February 2017

Physical design Interview Question part 8

What are well tap cells, what are end cap cells and its usage
What are the inputs to CTS
What sanity checks are to be done in SDC file
What is de-rating
What is clock skewing and what is a useful skew
how many clocks are used in your project
what is the maximum frequency
what is latency
what is clock generation point, clock distribution point, clock end point
why is the setup check in next cycle and hold checked at same time
what is the width and spacing rules for clocks
what are the NDR for clocks
what are NDR and DRC checks done at each stage of project
what is OCV, antenna violation and what are measures taken
what is antenna ratio
what is RC extraction and when do you do this
if you have congestion after CTS and you are not allowed to change the placement how do you proceed
does set up fixes cause hold issues and vice versa
what is slack
what happens if there is any floating pin and it is left without any care
what is electro migration
what is signal integrity and cross talk
what are the preventions taken at each stage to resolve cross talk issue
what is shielding
what is Physical verification, formal verification
what are the DRC checks made in project
what is LVS what information is obtained from LVS
what are the signoff checks and which tools are used for it
what are the inputs to STAR RC and prime time
what is cloning
what happens if any of the input files are missed to IC compiler
what is RTL , gate level differences
What does synthesis team do?
What are libraries needed for tool, what is difference between logic and physical library
What is a UPF file, is it used in your project
What ae filler cells
What are ECOs , how many Eco are implemented
What ae the DRC fixed
What is low power design
What is clock and power gating

1 comment:

  1. Interesting and informative questionnaire.Your information and understanding level is so high and good.You can completely manage and it can be productive for so many.Good luck.