Saturday, 20 February 2016

Physical Design Interview Question Part 1

  1. Explain concept of   cross talk? 
  2. How can you overcome cross talk problem? 
  3. what is shielding? how it avoid avoids crosstalk problem? 
  4. how spacing h reducing crosstalk noise? 
  5. Why double spacing and multiple vias are used related to clock? 
  6. where do you insert buffer to avoid crosstalk? how buffer insertion solve the problem?
  7. Difference between Chip Design and Block level design? 
  8. What are the ways to place macros in a full chip design? 
  9. what are the differences between Hierarchical Design and flat design? 
  10. Why 500 MHz clock design is complex than 48Mhz design? 
  11. What all tools used in physical verification? 
  12. what are the inputs you will give in physical verification
  13. how will you solve the congestion between two macros? 
  14. what all parameters you will consider while estimating die size? 
  15. What is each macro size and number of standard cell count? 
  16. Depends on your design. 
  17. What are the input needs for your design?  
  18. What does SDC (Synopsys design contraint)  file contains? 
  19. how will give Clock definitions ?
  20. what are timing Timing exception, how will you constraint them?
  21. what is Input and Output delays, what are prime time  commands for it?
  22. How did you do power planning? 
  23. Explain, how will you find number of power pad and IO power pads? 
  24. How the  number of power straps calculate? 
  25. How to find total power of chip, What are the problems you can  faced with respect to timing? 
  26. what is  setup and hold problem, how will you solve it?
  27. which is preferable layer for clock routing and why? 
  28. what do you mean by IR drop problem, how will you overcome by this problem? 
  29. what is  antenna effect, how does it impact the and how would you resolve antennae effect problem? 
  30. How are the PVT conditions? Describe using graph?
  31. Describe the physical design flow?
  32. what all the  and inputs and outputs for each step of physical design? 
  33. What is cell delay and net delay, how will you reduce this delays? 
  34. What are  the different timing delay models available? 
  35. What is wire load model (WLM)?  
  36. Why higher metal layers are preferred for power? 
  37. What do you mean by logic optimization techniques, how it will work?
  38. what is slack, how will you calculate slack?
  39. what are the parameters on which slack depends on?
  40. What do you mean by of negative slack, how will u make it positive?  
  41. What is EM and it effects? 
  42. What are types of routing ?  
  43. What do you mean by clock latency? what are the  types of clock latecies? 
  44. What is track assignment in routing stage? 

1 comment:

  1. Tks very much for your post.

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