- What should we do if we want to include analog macro in the extraction?
- Type of techniques around periphery of block to maintain timing.
- Techniques to minimize number of hold buffers.
- What point in design, we look at hold timing?
- Were design blocks multimode?
- Single set or multiple set of constraints (for clock)
- Any experience in timing closure/ECO?
- What format did you get your ECO file? In Tcl script format or Graphical based format?
- Who set up primetime tool for design (like setting constraints)?
- For STA, do you need to create constraints for different operating modes like system mode or test mode?
- Techniques for I/O interface timing closure.
- Experience with Multimode/Single mode and multi corner blocks?
- Did top level person provide Tcl scripts?
- PTSI like (DMSA, fixing timing from PT, fixing transition from PT)
- DMSA --> Distributed Multi Scenario Analysis (flow used in PT for timing ECO).
- Have you done crosstalk analysis in your design?
- If you have undriven flops during check timing report, how will you proceed?
- If you have timing violations from a memory where the logic count is proper and constraints are also validated, how do you solve this?
- How do you fix Noise violation?
- How does upsizing of driver of victim help to fix noise violation?
Saturday, 20 February 2016
STA Interview Question Part 3
Posted by Akshay at 23:13