Basics of IC Compiler

Basics of IC Compiler

The IC Compiler tool uses logic libraries to provide timing and functionality information for all
standard cells. In addition, logic libraries can provide timing information for hard macros, such
as RAMs. The tool supports logic libraries that use nonlinear delay models (NLDMs) and
Composite Current Source (CCS) models and automatically selects the timing models to use,
based on the contents of the logic libraries. If the logic libraries contain a mixture of both NLDM
and CCS models, by default, the tool uses the CCS capacitance and timing data; you can control
this by setting the lib_pin_using_cap_from_ccs and lib_cell_using_delay_from_ccs variables
before loading the libraries.

The link libraries are the logic libraries used to resolve cell references when the tool links the
design.The first library specified in the link_library variable is the main library.

The target libraries are the logic libraries that the tool uses to perform physical optimization.

The Milkyway reference libraries contain timing constraints and physical information about
the standard cells and macro cells in your logic library. In addition, these reference libraries
define the placement unit tile. The technology file provides technology-specific information,
such as the name and characteristics of each metal layer.

The physical library information is stored in the Milkyway design library. For each cell, the
Milkyway design library contains several views of the cell, which are used for different
physical design tasks. Commonly used views include

• The layout (CEL) view
• The place and route (FRAM) view
• The metal fill (FILL) view
• The power and ground connectivity (CONN) view

The error (ERR) view

If a Milkyway library does not already exist for your design, you need to create one and open it.

> Creating a Milkyway Design Library:

To create a Milkyway design library, use the create_mw_lib command;

Before working with the design, you must specify the Milkyway reference libraries used for the design. You can do this when you create the Milkyway design library with the create_mw_lib command or you
can do it later by using the set_mw_lib_reference command.

Note:

You can use the set_mw_lib_reference command to define the Milkyway reference libraries
associated with a Milkyway design library only when the Milkyway design library is closed. If the
design library is open, close it with the close_mw_lib command before defining the reference libraries.

> You can change the technology file and Milkyway reference libraries associated with your design
library.

Note: You can change the physical library information only when the Milkyway design library is closed.

> Before you process your design, you should use the check_library command to ensure that the logic libraries and physical libraries are correct and consistent.

By default, the check_library command performs consistency checking between the logic
libraries specified in the link_library variable and the physical libraries referenced in the current
Milkyway design library. If the check_library command reports any inconsistencies, you must fix
them before you process your design.

> The IC Compiler tool can read designs in Milkyway, .ddc, or ASCII (Verilog) format.

1) Reading a Design in Milkyway Format:

• The unit settings in the Milkyway design must be consistent with the unit settings in the main library (the first library in the link_library definition). To see the main library unit settings, use the report_lib command. To see the Milkyway design library unit settings, use the report_units command. The Milkyway design contains the floorplan information and timing constraints previously set on the design, so you do not need to annotate this information separately. 2) Reading a Design in .ddc Format:
• Readthe.ddcfileforthedesignbyusingtheimport_designscommand;Annotatethefloorplaninformationonthedesign.The .ddc design contains the scan chain information and timing constraints previously set on the design, so you do not need to annotate this information separately. If you are using a bottom-up flow, you must have FRAM views for all blocks in the top-level design.

> Note: Before reading the floorplan file, create the logical power and ground connections by using the derive_pg_connection command

> The tool maintains the SCANDEF data that describes scan chain characteristics and constraints, as well as the scan-stitched netlist. The netlist and SCANDEF data must be consistent with each other. To validate their consistency, use the check_scan_chain command.

> Validating the Floorplan Information ：

• Before running the place_opt command, run the check_physical_design command with the -stage pre_place_opt option.
  icc_shell> check_physical_design -stage pre_place_opt 
• Before running the clock_opt command, run the check_physical_design command
  with the -stage pre_clock_opt option.
  icc_shell> check_physical_design -stage pre_clock_opt 
• Before running the route_opt command, run the check_physical_design command with the -stage pre_route_opt option.
  icc_shell> check_physical_design -stage pre_route_opt 

> To validate the integrity of the design database, run the check_database command. By default, the check_database command verifies that

• The power and ground network is consistent
• There are no logical connections to physical-only cells
• The UPF data is consistent, if it exists
• The design has been uniquified and contains hierarchy preservation data
  To perform only the logical checks, use the -netlist option. To perform only the physical checks, use the -physical option. You can increase the verbosity of the generated messages by setting the -verbosity option to medium or high (the default is low).
  You should run the check_database command

• After reading a design in ASCII format using the read_def command
• Before running application commands, such as change_names, create_block_abstraction, place_opt, clock_opt, and route_opt. This can help save runtime in the case of a data error
• Before using the write_verilog command.

> use the derive_pg_connection command  to creates the logical power and ground connections for leaf cells, hierarchical cells, and physical-only cells in both single-voltage and multivoltage designs.

• To show the logical power and ground connections made by the derive_pg_connection command, use the report_cell_physical –connections command. You should rerun the derive_pg_connection command whenever the power and ground connections have changed, such as
  • After design planning
  • After using logic ECO to modify the design
  • After chip-finishing tasks

• If the design does not yet have power and ground ports, use the -create_ports top option to create these ports.

• If the design already has logical power and ground connections but you want to regenerate these connections, use the remove_pg_network -top command to remove the existing power and ground network before you run the derive_pg_connection command. By default, the derive_pg_connection command does not change existing power and ground pin connections. To reconnect the power and ground pins, use the -reconnect option when you run the derive_pg_connection command.

Note that the -reconnect option of the derive_pg_connection command does not reconnect tie-off nets.

》TLUPlus is a binary table format that stores the RC coefficients. The TLUPlus models enable accurate RC extraction results by including the effects of width, space, density, and temperature on the resistance coefficients.

• The map file, which matches the layer and via names in the Milkyway technology file with the names in the ITF file.

For multicorner-multimode designs, use the set_tlu_plus_files command to specify the TLUPlus files for each scenario. The set_tlu_plus_files command only applies to the current scenario.

After specifying the TLUPlus files, you should validate them by running the check_tlu_plus_files command.

> The operating conditions of a design include the process, voltage, and temperature parameters under which the chip is intended to operate. The tool analyzes and optimizes the design under the conditions you specify.

For multicorner-multimode designs, specify an operating condition for each scenario in the design.

Note: The link path should contain only the maximum library.

To find out which libraries are defined as the maximum and minimum libraries, use the list_libs command. In the generated report, the uppercase letter “M” appears next to the maximum library, and the lowercase letter “m” appears next to the minimum library.

> Advanced on-chip variation (AOCV) is an optional method of accuracy improvement that determines varying derating factors for different clock paths based on the path lengths.

Setting Timing Constraints

At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input delay or output delay for each I/O port. This requirement ensures that all signal paths are constrained for timing.

To model the clock tree effects for placement before running clock tree synthesis, you should also define the uncertainty, latency, and transition constraints for each clock by using the set_clock_uncertainty, set_clock_latency, and set_clock_transition commands.

The tool does not optimize paths that are not constrained for timing. Before proceeding, use the check_timing command to verify that all paths are constrained. If the check_timing command reports unconstrained paths, run the report_timing_requirements command to verify that the unconstrained paths are false paths (the check_timing command considers false paths unconstrained).

remove_ideal_network -all  This command removes ideal_network attributes, latencies, and transition times.

For multicorner-multimode designs, you must define timing constraints for each scenario.

Selecting the Delay Calculation Method

By default, the tool uses the Elmore delay model for preroute delay calculation and the Arnoldi delay model for routed clock and postroute delay calculation. To change the delay calculation model, use the set_delay_calculation_options command.

For preroute delay calculation, the tool computes delays based on estimated parasitic data for the nets. You can choose either Elmore or asymptotic waveform evaluation (AWE) as the delay model. The AWE delay model provides better accuracy and better correlation with postroute delay calculation.

For routed clock delay calculation and for postroute delay calculation, you can choose either Arnoldi or Elmore as the delay model. The Arnoldi delay model provides better accuracy and better correlation with PrimeTime delay calculation, especially for smaller geometries and for highly resistive nets.

You can use the compare_delay_calculation command to compare Elmore and Arnoldi results of sample delay calculations in your design. If the results are similar between the two methods, use the faster Elmore method. Otherwise, if you need the additional accuracy, use the Arnoldi method.

By default, the tool does not include crosstalk delta delays in the delay calculations. To extract coupling capacitances and include crosstalk delta delays in the postroute delay calculations, enter the following command:

icc_shell> set_si_options -delta_delay true 

Defining the Buffer Strategy for Optimization

During the optimization step, the place_opt command introduces buffers and inverters to fix timing and DRC violations. However, this buffering strategy is local to some critical paths. The buffers and inverters that are inserted might become excess later because critical paths change during the course of optimization. You can reduce the excess buffer and inverter counts after place_opt by using the set_buffer_opt_strategy command, as shown in the following example:

icc_shell> set_buffer_opt_strategy -effort low
This buffering strategy does not degrade the quality of results (QoR).

If you use the set_dont_use command to set the dont_use attribute on cells BUF1 and BUF2 , the tool uses cells BUF1 and BUF2 to fix hold violations, but not setup and DRC violations.

Enabling Tie Cell Insertion

A tie cell is a special-purpose standard cell whose output is constant high or constant low and is used to hold the input of another cell at the given constant value.

High-Fanout Net Synthesis

During placement and optimization, the IC Compiler tool does not buffer clock nets as defined by the create_clock command, but it does, by default, buffer other high-fanout nets, such as resets or scan enables, using a built-in high-fanout synthesis engine.

The high-fanout synthesis engine does not buffer nets that are set as ideal nets or nets that are disabled with respect to design rule constraints.

Inserting Port Protection Diodes

The IC Compiler tool can automatically insert protection diodes on subdesign ports to prevent antenna violations at the top level. You insert the port protection diodes after floorplanning but before starting placement.

Performing Placement and Optimization 

The place_opt command performs coarse placement, high-fanout net synthesis, physical optimization, and legalization. In addition, it can perform clock tree synthesis, scan chain reordering, and power optimization.

Performing Power Optimization 

Leakage dissipation is low when the threshold voltage is high and vice versa. Moreover, switching delay is increased when threshold voltage is high. So, using high-threshold-voltage cells to reduce the leakage can violate the timing constraints of the design. If the logic library supports cells with multiple threshold voltages, using cells with a lower threshold voltage for timing-critical paths and cells with a higher threshold voltage for other paths can reduce the leakage power without violating the delay.

During leakage-power optimization, the tool improves the leakage power only if it does not degrade timing.

Creating Multibit Register Banks

You can use the register banking flow to merge single-bit registers to form multibit register banks during placement and optimization.

Creating multibit register banks reduces

• The design area due to the smaller area of one multibit register bank compared to that of multiple single-bit registers
• The clock tree power consumption due to the smaller number of clock tree buffers

Analyzing the Placement Area Utilization

The default utilization is calculated as: (non-fixed_standard_cell_area + fixed_standard_cell_area) / (total_area – blocked_area)

whereas non-fixed-only utilization is calculated as: (non-fixed_standard_cell_area) / (total_area – fixed_standard_cell_area – blocked_area) 

Reporting Quality-of-Results

You can generate a report on the quality of results (QoR) for the design in its current state by using the create_qor_snapshot command (or by choosing Timing > Create QoR Snapshot in the GUI). This command measures and reports the quality of the design in terms of timing, design rules, area, power, congestion, clock tree synthesis, routing, and so on.

Performing Magnet Placement

To improve congestion for a complex floorplan or to improve timing for the design, you can use magnet placement to specify fixed objects as magnets and have the tool move their connected standard cells close to them.

For best results, perform magnet placement before standard cells are placed.

Magnet placement allows cells to be overlapped by default. To prevent overlapping of cells, you can set the magnet_placement_disable_overlap variable to true, changing it from its default of false.

Refining Placement

If your design shows large timing or violations after you run the place_opt command, adjust the place_opt options and rerun place_opt.

If your design shows small timing or violations after you run place_opt, run psynopt to fix these violations.

If your design has congestion violations after you run place_opt, rerun place_opt with high-effort congestion reduction (-congestion option). If your design still has congestion violations, you can refine the placement to fix these violations.