Question which were asked on 22nd dec session (doubts clearing session)

1. Difference between flat and hierarchical design?
2. What is the need for sanity checks at floorplan stage?
3. Explanation of flipchip?
4. How can we decide no of routing layers in a design? Does more no of routing layers beneficial.
5. Difference between drive strength and fanout.
6. For specific corner can a path have both setup and hold violation?
7. Why do we have no of routing layers better or worse?
8. What is functional ECO?
9. Difference SDC file as an input to floor planning although we don’t do timing analysis after floor planning?
10. How to decide max transition on clock and data?
11. What is RDL layer?
12. Two clock paths coming from same PLL will always be synchronous or asynchronous? Or are there different conditions attached to it.
13. Why do we need driving cell for input ports and load for the output ports?
14. Is there any difference between tie cells and level shifters?
15. Why setup is only considered for worst case? and Hold for best case? and What will happen if reverse is done?
16. Explanation regarding capture and launch clock.
17. Difference between HFNS and CTS.  
18. how std cells are placed? With complete explanation?
19. how to resolve unsigned nets in the synthesis stage?
20. how to resolve max tran and max cap vailotions?
21. implicite and explicit exceptions in cts stage?
22. Input files based on Physical Design (Indeep and explain with those files?
23. Synchronizer Logic With Example?
24. Frequency divider for 3,4,5,6,7,8?
25. When we ar eworking  90nm or other tech  how to change  one technology to another technology or else for given technology is fixed we can't  change for a same project
26. how to fix drc
27. is drc and crpr related

How many macros and standard cell were there in your block?

Answer to this question is purely on the design specific, bu there are blocks without macros also, which is called purely standard cell cells blocks. As number of macros increased, analysis in the floor plan also increases, below are some checks which you have to do while handling large number of macro

1. Legalization of macros

2. connectivity of macros to standard cells, other macro and ports, ignoring of this point may cause the congestion and timing violation

3. while arranging the macros in floorplan consider macro to macro communication also

4. always keep some channel between the macro, in later stages this will help in hold buffering,

Physical Design Interview Part 7

• Tell me about yourself in brief
• Inputs to PNR
• Do you have knowledge on synthesis
• What are the validations and sanity checks you do on the outputs received from synthesis team
• Which file will you need to check if you see black box in the screen
• Which file you need to check if you see any floating pins and whom should you report in such case
• What does .tf file, .db file, .sdc file, .spef file .v files include
• What is floor plan and what is done as part of floor plan
• How do you fix placement of RAMs 
• What is utilization factor and Area
• What is fly line analysis
• How do you decide the spacing between the macros and standard cells
• What are tie cells and can the size of array of tie cells be either increased or decreased? –No
• Which layers are preferred for power routing and why?
• Which is preferred to be the outer most layer or top layer
• What is the UF in floor plan
• What is the skew achieved in your project and what is the allowed skew
• What is local skew and global skew difference
• What are the tools used for PNR
• What is high fan out synthesis
• What is placement and what do we do in this step
• What is NLDM
• What is congestion and timing closure
• What special physical cells are used  in your project
• Purpose of power domains, level shifter cells, isolation cells, Always on cell
• Where do we use Always On buffers
• How is drive strength and delay relation
• What is inversion temperature
• How is delay and temperature relation
• How is threshold voltage and temperature variations related
• What happens when you do congestion driven placement
• Where are the buffers placed? What is the functionality of buffers
• How do buffers speed up the signal in data or in clock even if it adds delay to the path
• What is set up and hold violation
• What are the ways to fix the set up violation
• Ways to fix hold violation
• What is STA and which tool is being used for STA
• What are the optimizations done in placement stage
• What are the power domains in your project
• What is switchable power domain

Questions Related to Power Planning, IR drop and Low power

1.  what is powerplanning, How you use to do i. Power estimation ii. power pads estimation (core & IO) iii. core ring width calculation iv. EMIR v. SSO 
2.  What are preroutes in your design? 
3.  How to power route multiVDD design?
4. Power domains, partitioning, power routing for multi domains, placement of power switches?
5. What are the various views of a macro or a cell?
6.  What is the macro placement guidelines?
7.  What all checks will you perform after Floor planning?
8.  What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
9. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
10. How did you define your power structure for full chip? 
11. How will you start power planning for your design?                                                                                                                                                                                                                      EMIR & low power:
12. How power is related with clock frequency? 
13. Can we achieve lower power with more than one voltage supply?
14. Different low power techniques?
15. methods of leakage reduction? 
16. What are the vectors of dynamic power? 
17. How can you reduce dynamic power? 
18. If you have both IR drop and congestion how will you fix it? 
19. Is increasing power line width and providing more number of straps are the only 
20. solution to IR drop? 
21. Why higher metal layers are preferred for Vdd and Vss? 
22. What is IR drop? How it affects timing? 
23. What is EM and it effects? how to resolve EM?
24. Techniques to avoid IR problems? Dynamic & Static
25. Do we have inactive blocks that we can shut off to reduce leakage power?
26. What are Retention registers?
27. Give the various techniques you know to minimize power consumption for CMOS logic? 
28. Give the expression for CMOS switching power dissipation? 
29. List out the factors affecting power consumption on a chip? 
30. Any custom routes of analog/power? What were the requirements of custom routes?
31. Any experience in low power techniques?
32. Any experience with multi Vt libraries?
33. What is total Static & dynamic power consumption in your design?

Physical Design (Power planning) Interview Question Part 5

1. . How will you do power planning? 
2.  Power estimation
3.  power pads estimation (core & IO) 
4. core ring width calculation
5. EMIR considerations
6. SSO considerations
7. What are preroutes in your design? 
8. How to power route multiVDD design?
9.  Power domains, partitioning, power routing for multi domains, placement of power switches?
10.  What are the various views of a macro or a cell?
11.  What is the macro placement guidelines?
12. What all checks will you perform after Floor planning?
13. What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
14. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to center, what will be your approach?
15. How did you define your power structure for full chip? 
16. How will you start power planning for your design?
17. EMIR & low power:
18. How power is related with clock frequency? 
19. Can we achieve lower power with more than one voltage supply?
20. Different low power techniques?
21. methods of leakage reduction? 
22. What are the vectors of dynamic power? 
23. How can you reduce dynamic power? 
24. If you have both IR drop and congestion how will you fix it? 
25. Is increasing power line width and providing more number of straps are the only solution to IR drop? 
26. Why higher metal layers are preferred for Vdd and Vss? 
27. What is IR drop? How it affects timing? 
28. What is EM and it effects? how to resolve EM?
29. Techniques to avoid IR problems? Dynamic & Static
30. Do we have inactive blocks that we can shut off to reduce leakage power?
31. What are Retention registers?
32. Do we have blocks that can run at slower rate in certain modes? Can we reduce the 
33. voltage during those modes?
34. Give the various techniques you know to minimize power consumption for CMOS logic? 
35. Give the expression for CMOS switching power dissipation? 
36. List out the factors affecting power consumption on a chip? 
37. Any custom routes of analog/power? What were the requirements of custom routes?
38. Any experience in low power techniques?
39. Any experience with multi Vt libraries?
40. What is total Static & dynamic power consumption in your design?

Frequently Asked Question Part 2

                                                                                                                           Previous Page

* What is signal integrity? How it affects Timing?
* What is IR drop? How to avoid IR drop .how it affects timing?
* What is EM and it effects?
* What is floor plan and power plan?
* What are types of routing?
* What is a grid .why we need and different types of grids?
* What is core and how u will decide w/h ratio for core?
* What is effective utilization and chip utilization?
* What is latency? Give the types?
* What is LEF?
* What is DEF?
* What are the steps involved in designing an optimal pad ring?
* What are the steps that you have done in the design flow?
* What are the issues in floor plan?
* How can you estimate area of block?
* How much aspect ratio should be kept (or have you kept) and what is the utilization?
* How to calculate core ring and stripe widths?
* What if hot spot found in some area of block? How you tackle this?
* After adding stripes also if you have hot spot what to do?
* What is threshold voltage? How it affect timing?
* What is content of lib, lef, sdc?
* What is meant my 9 track, 12 track standard cells?
* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
* What is setup and hold? Why there are ? What if setup violation fix and hold violation fixtures?
* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
* How R and C values are affecting time?
* How ohm (R), fared (C) is related to second (T)?
* What is transition? What if transition time is more?
* What is difference between normal buffer and clock buffer?
* What is antenna effect? How it is avoided?
* What is ESD?
* What is cross talk? How can you avoid?
* How double spacing will avoid cross talk?
* What is difference between HFN synthesis and CTS?
* What is hold problem? How can you avoid hold time violations?
* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
* What is partial floor plan?
* What parameters (or aspects) differentiate Chip Design & Block level design??
* How do you place macros in a full chip design?
* Differentiate between a Hierarchical Design and flat design?
* Which is more complicated when u have a 48 MHz and 500 MHz clock design?
* Name few tools which you used for physical verification?
* What are the input files will you give for primetime correlation?
* What are the algorithms used while routing? Will it optimize wire length?
* How will you decide the Pin location in block level design?
* If the routing congestion exists between two macros, then what will you do?
* How will you place the macros?
* How will you decide the die size?
* If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
* If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
* In your project what is die size, number of metal layers, technology, foundry, number of clocks?
* How many macros in your design?
* What is each macro size and no. of standard cell count?
* How did u handle the Clock in your design?
* What are the Input needs for your design?
* What is SDC constraint file contains?
* How did you do power planning?
* How to find total chip power?
* How to calculate core ring width, macro ring width and strap or trunk width?
* How to find number of power pad and IO power pads?
* What are the problems faced related to timing?
* How did u resolve the setup and hold problem?
* If in your design 10000 and more numbers of problems come, then what you will do?
* In which layer do you prefer for clock routing and why?
* If in your design has reset pin, then it’ll affect input pin or output pin or both?
* During power analysis, if you are facing IR drop problem, then how did u avoid?
* Define antenna problem and how did u resolve these problem?
* How delays vary with different PVT conditions? Show the graph.
* Explain the flow of physical design and inputs and outputs for each step in flow.
* What is cell delay and net delay?
* What are delay models and what is the difference between them?
* What is wire load model?
* What does SDC constraints has?
* Why higher metal layers are preferred for Vdd and Vss?
* What is logic optimization and give some methods of logic optimization.
* What is the significance of negative slack?
* How the width of metal and number of straps calculated for power and ground?
* What is negative slack ? How it affects timing?
* What is track assignment?
* What is grided and gridless routing?
* What is a macro and standard cell?
* What is congestion?
* Whether congestion is related to placement or routing?
* What are clock trees?
* What are clock tree types?
* Which layer is used for clock routing and why?
* What is cloning and buffering?
* What are placement blockages?
* How slow and fast transition at inputs effect timing for gates?
* What is antenna effect?
* What are DFM issues?
* What is .lib, LEF, DEF, .tf?
* What is the difference between synthesis and simulation?
* What is metal density, metal slotting rule?
* What is OPC, PSM?
* Why clock is not synthesized in DC?
* What are high-Vt and low-Vt cells?
* What corner cells contains?
* What is the difference between core filler cells and metal fillers?
* How to decide number of pads in chip level design?
* What is tie-high and tie-low cells and where it is used

Physical Design Course for beginners

Detailed list of Topics, Note this topics will be timely updated as per requirement, any feedback and suggestions are welcome (please write on comment section or send mail us to vlsijunction@gmail.com)

List of Topics
About this blog

PreRequisite

• CMOS Fundamentals
• Wafer Fabrication Techniques
• Basic Linux Commands
• Digital Electronics Fundamentals 

Physical Design Flow

• Moore's Law
• Basic Synthesis Flow
• Physical Design Introduction
• Physical Design Flow
• Important Input Files
• Sanity Checks
• Floor Planning
• Power Planning Basics
• Placement
• Routing
• CTS
• STA
• Physical Verification

FloorPlannig topics

• Blockages
• Aspect Ratio
• Design Netlist
• Some Basic Rules For Placing Macros
• IO Placement / Pin placement
• Core Utilization
• Die Area calculation
• Design Exchange Format (DEF) Files
• Library Exchange Format (LEF) Files
• Macro Placement Tips

Power planning

• Calculation Related to power Planning
• Detailed Power Planning Concept

Low Power Design Techniques

• Power Gating
• Low Power Design

Placement

• Scan Chain Reordering
• Types of Cell
• Level Shifter
• Isolation Cell
• Enable Level Shifter
• Retention Flops
• Always ON cells
• Power Gating Switches/MTCMOS switch
• 12 Track Vs 9 Track Standard Cell

CTS

• How To fix Setup time Violation
• How To Fix Hold Time Violations
• Non Default Rules (NDR)
• HVT LVT SVT Cells
• Crosstalk
• Clock Buffer VS Normal Buffer

 Routing

• How to Control Congestion

STA

1. Setup Time
2. Hold Time
3. Slack
4. Clock Latencies
5. Clock Skew
6. Recovery and Removal Time
7. Timing Exceptions
8. Onchip Variation (OCV)
9. Advance Onchip Variation
10. Signal Integrity
11. Statistical static timing analysis
12. Topics Covered in Static Timing Analysis (STA)
13. Parametric On chip variation (POCV)
14. Asynchronous Path
15. Input To STA Tools
16. STA vs DTA
17. Timing Paths
18. Propagation Delay Calculations
19. Clock Gating
20. Jitter
21. Unateness
22. Signal Integrity Effects
23. Virtual Clock

Sign Off Check

Physical verication

STA

IR Drop

DFM

• Double Patterning
• Electrostatic Discharge
• VIA Concept
• Antennae Effect
• Electromigration

Tools Guide and References

• Scripts used in IC Compiler
• IC Compiler User guide

Interview Questions

Physcial Design

• Physical Design Interview Question Part 1
• Physical Design Interview Question Part 2
• Physical Design Interview Question Part 3
• Physical Design Interview Question Part 4
• Physical Design Interview Question Part 5
• Physical Design Interview Question Part 6
• Physical Design Interview Question Part 7
• Physical Design Interview Question Part 8

Career In Physical Design

• Companies works in VLSI

References

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Design Exchange Format (DEF) Files

DEF Files

A specification for representing logical connectivity and physical layout of and integrated circuit in ASCII format

A DEF file is used to describe all the physical aspects of a design, including 

- Die size

- Connectivity 

- Physical location of cells and macros on the chip. 

It contains floor-planning information such as 

- Standard cell rows, groups

- Placement and routing blockages

- Placement constraints

- Power domain boundaries. 

It also contains the physical representation for pins, signal routing, and power routing, including rings and stripes.